xlcosim_dac_test_modelsim.vhd

使用ＭＡＴＬＡＢ工具

library IEEE;
use IEEE.std_logic_1164.all;


entity xlcosim_dac_test_modelsim is 
  port (
    dac_test_black_box_din: in std_logic_vector(17 downto 0);
    dac_test_black_box_fltsel: in std_logic;
    dac_test_black_box_rstn: in std_logic;
    dac_test_black_box_dout: out std_logic_vector(17 downto 0)
  );
end xlcosim_dac_test_modelsim;

architecture structural of xlcosim_dac_test_modelsim is
  component dac_test_black_box_wrapper
    port (
      clk: in std_logic;
      ce: in std_logic;
      clk_1: in std_logic;
      ce_1: in std_logic;
      din: in std_logic_vector(17 downto 0);
      fltsel: in std_logic;
      rstn: in std_logic;
      dout: out std_logic_vector(17 downto 0)
    );
  end component;
  component xlcosim_dac_test_modelsim_clk_drvr
    port (
      clk: out std_logic;
      ce_1: out std_logic;
      ce_2: out std_logic
    );
  end component;

  signal ce_1_net: std_logic;
  signal ce_2_net: std_logic;
  signal clk_net: std_logic;
  signal dac_test_black_box_din_net: std_logic_vector(17 downto 0);
  signal dac_test_black_box_dout_net: std_logic_vector(17 downto 0);
  signal dac_test_black_box_fltsel_net: std_logic;
  signal dac_test_black_box_rstn_net: std_logic;

begin
  dac_test_black_box_din_net <= dac_test_black_box_din;
  dac_test_black_box_fltsel_net <= dac_test_black_box_fltsel;
  dac_test_black_box_rstn_net <= dac_test_black_box_rstn;
  dac_test_black_box_dout <= dac_test_black_box_dout_net;

  clock_driver: xlcosim_dac_test_modelsim_clk_drvr
    port map (
      clk => clk_net,
      ce_1 => ce_1_net,
      ce_2 => ce_2_net
    );
  dac_test_black_box: dac_test_black_box_wrapper
    port map (
      clk => clk_net,
      ce => ce_1_net,
      clk_1 => clk_net,
      ce_1 => ce_2_net,
      din => dac_test_black_box_din_net,
      fltsel => dac_test_black_box_fltsel_net,
      rstn => dac_test_black_box_rstn_net,
      dout => dac_test_black_box_dout_net
    );
end structural;