代码搜索:modelSim

找到约 1,834 项符合「modelSim」的源代码

代码结果 1,834
www.eeworm.com/read/452301/7442120

do cardbus_5632_modelsim_post.do

#------------------------------------------------------------------------------ # # File : cardbus_5632_modelsim_post.do # Last Modification: 06/26/2001 # # Created In SpDE Version: SpDE 9.5.3 #
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do cardbus_5632_modelsim_post.do

#------------------------------------------------------------------------------ # # File : pci5632_280modelsim_post.do # Last Modification: May/17/2002 # # Created In SpDE Version: SpDE 8.22 # A
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vhd modelsim testbench vhdl参考模板.vhd

-- VHDL Test Bench Created from source file fifo_new.vhd -- 10:13:22 04/05/2005 -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for
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txt debussy和modelsim协同仿真.txt

1、编辑modelsim根目录下的modelsim.ini文件,将; Veriuser = veriuser.sl 更换为Veriuser = novas_fli.dll。 2、将C:\Novas\Debussy\share\PLI\modelsim_fli54\WINNT下的novas_fli.dll 拷贝至C:\Modeltech_6.1d\win32中 3、将C:\Novas\D
www.eeworm.com/read/137627/13307853

xrf trans4_16_modelsim.xrf

vendor_name = ModelSim source_file = 1, D:/Quartus/trans4_16/trans4_16.vhd design_name = trans4_16 instance = comp, in4_a0_a_aI, in4[0], trans4_16, 1 instance = comp, in4_a3_a_aI, in4[3], trans4_1