代码搜索：modelSim

找到约 1,834 项符合「modelSim」的源代码

代码结果 1,834
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/328695/3439229

xrf bcd_decoder_modelsim.xrf

vendor_name = ModelSim source_file = 1, D:/my_eda/bcd_decoder/bcd_decoder.vhd source_file = 1, D:/my_eda/bcd_decoder/bcd_decoder.vwf design_name = bcd_decoder instance = port, i0, i[0], bcd_decode
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www.eeworm.com/read/326943/3465606

mgf 0modelsim_work.mgf

V 000040 12 269 1071731857729 PRIM_DFFE E PRIM_DFFE VERILOG UDP L VL; U VL.VERILOG_LOGIC; P Q _out reg V Q - - - - P ENA _in wire V ENA - - - - P D _in wire V D - - - - P CLK _in wire V CLK - - - - P
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www.eeworm.com/read/326943/3465608

mgf 4modelsim_work.mgf

I 000035 56 942 1071731857737 dffe (_unit dffe (_specify (_specparam TRSU integer 0) (_specparam TREN integer 0) (_specparam TREG integer 0) (_specparam TRCL integer 0) (_specparam TRH inte
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www.eeworm.com/read/301574/3837630

mgf 0modelsim_work.mgf

V 000040 12 269 1071731857729 PRIM_DFFE E PRIM_DFFE VERILOG UDP L VL; U VL.VERILOG_LOGIC; P Q _out reg V Q - - - - P ENA _in wire V ENA - - - - P D _in wire V D - - - - P CLK _in wire V CLK - - - - P
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www.eeworm.com/read/301574/3837632

mgf 4modelsim_work.mgf

I 000035 56 942 1071731857737 dffe (_unit dffe (_specify (_specparam TRSU integer 0) (_specparam TREN integer 0) (_specparam TREG integer 0) (_specparam TRCL integer 0) (_specparam TRH inte
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www.eeworm.com/read/294643/3916245

xrf control8080_modelsim.xrf

vendor_name = ModelSim source_file = 1, E:/电子设计竞赛/verilog/模块/测试版8080/inter_8080.v source_file = 1, E:/电子设计竞赛/verilog/模块/测试版8080/control8080.v design_name = control8080 instance = comp, \data[0]~I
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www.eeworm.com/read/285694/4047536

mgf 0modelsim_work.mgf

V 000040 12 269 1071731857729 PRIM_DFFE E PRIM_DFFE VERILOG UDP L VL; U VL.VERILOG_LOGIC; P Q _out reg V Q - - - - P ENA _in wire V ENA - - - - P D _in wire V D - - - - P CLK _in wire V CLK - - - - P
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www.eeworm.com/read/285694/4047538

mgf 4modelsim_work.mgf

I 000035 56 942 1071731857737 dffe (_unit dffe (_specify (_specparam TRSU integer 0) (_specparam TREN integer 0) (_specparam TREG integer 0) (_specparam TRCL integer 0) (_specparam TRH inte
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www.eeworm.com/read/442519/1759602

xrf samul1_modelsim.xrf

vendor_name = ModelSim source_file = 1, E:/VHDL programs/SAmul1/SAMul1.vhd source_file = 1, E:/VHDL programs/SAmul1/SAMul1.vwf design_name = SAMul1 instance = comp, \en~I\, en, SAMul1, 1 instance
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www.eeworm.com/read/427629/1968975

xrf ram_control_modelsim.xrf

vendor_name = ModelSim source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/quartus/RAM_36.v source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v source_file
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