ram_control_modelsim.xrf

压缩包内包含了：FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！

vendor_name = ModelSim
source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/quartus/RAM_36.v
source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
source_file = 1, c:/altera/quartus50/libraries/megafunctions/stratix_ram_block.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/lpm_mux.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/lpm_decode.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/aglobal50.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altsyncram.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/a_rdenreg.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altrom.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altram.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altdpram.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/altqpram.inc
source_file = 1, c:/altera/quartus50/libraries/megafunctions/cbx.lst
source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/quartus/db/altsyncram_e181.tdf
design_name = ram_control
instance = comp, \clk~I , clk, ram_control, 1
instance = comp, \rst~I , rst, ram_control, 1
instance = comp, \countwr[0]~I , countwr[0], ram_control, 1
instance = comp, \countwr[1]~I , countwr[1], ram_control, 1
instance = comp, \countwr[2]~I , countwr[2], ram_control, 1
instance = comp, \countwr[3]~I , countwr[3], ram_control, 1
instance = comp, \countwr[4]~I , countwr[4], ram_control, 1
instance = comp, \state~122_I , state~122, ram_control, 1
instance = comp, \state.STATE2~I , state.STATE2, ram_control, 1
instance = comp, \reduce_nor~22_I , reduce_nor~22, ram_control, 1
instance = comp, \reduce_nor~0_I , reduce_nor~0, ram_control, 1
instance = comp, \reduce_nor~1_I , reduce_nor~1, ram_control, 1
instance = comp, \wren~I , wren, ram_control, 1
instance = comp, \data[0]~61_I , data[0]~61, ram_control, 1
instance = comp, \data[0]~I , data[0], ram_control, 1
instance = comp, \data[1]~I , data[1], ram_control, 1
instance = comp, \data[2]~I , data[2], ram_control, 1
instance = comp, \wraddress[3]~I , wraddress[3], ram_control, 1
instance = comp, \rdaddress[0]~90_I , rdaddress[0]~90, ram_control, 1
instance = comp, \rdaddress[0]~I , rdaddress[0], ram_control, 1
instance = comp, \rdaddress[1]~I , rdaddress[1], ram_control, 1
instance = comp, \rdaddress[2]~I , rdaddress[2], ram_control, 1
instance = comp, \rdaddress[3]~I , rdaddress[3], ram_control, 1
instance = comp, \RAM_36|altsyncram_component|auto_generated|ram_block1a0 , RAM_36|altsyncram_component|auto_generated|ram_block1a0, ram_control, 1
instance = comp, \q[0]~I , q[0], ram_control, 1
instance = comp, \q[1]~I , q[1], ram_control, 1
instance = comp, \q[2]~I , q[2], ram_control, 1
instance = comp, \q[3]~I , q[3], ram_control, 1