代码搜索:modelSim
找到约 1,834 项符合「modelSim」的源代码
代码结果 1,834
www.eeworm.com/read/17761/757744
v sram_modelsim.v
`timescale 1ns / 1ps
module sram_test(clk,
rst,
data1,
addr1,
ce1,
we1,
oe1,
data2,
addr2,
ce2,
we2
www.eeworm.com/read/18154/777236
sav modelsim.ini.sav
[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3 = C:\Libero\Model\win32acoem/../actel/vlog/proasic3
presynth = presynth
syncad_vhdl_li
www.eeworm.com/read/18581/794766
xrf muxcntlr_modelsim.xrf
vendor_name = ModelSim
source_file = 1, C:/altera/davincievm_gamma2/muxcntlr/muxcntlr.vhd
design_name = muxcntlr
instance = comp, ATA_SEL_aI, ATA_SEL, muxcntlr, 1
instance = comp, V33_ATA_DMARQ_aI
www.eeworm.com/read/18752/800768
xrf myfifo_modelsim.xrf
vendor_name = ModelSim
source_file = 1, myfifo.bdf
source_file = 1, mydram.v
source_file = 1, wram.v
source_file = 1, watchdog.v
source_file = 1, ad_collect.v
source_file = 1, addr_code.v
sourc
www.eeworm.com/read/32279/881953
xrf led_modelsim.xrf
vendor_name = ModelSim
source_file = 1, D:/my_eda2/led/led.vhd
source_file = 1, D:/my_eda2/led/led.vwf
design_name = led
instance = comp, \Selector7~315_I\, Selector7~315, led, 1
instance = comp,
www.eeworm.com/read/39267/1124971
xrf led_modelsim.xrf
vendor_name = ModelSim
source_file = 1, D:/my_eda2/led/led.vhd
source_file = 1, D:/my_eda2/led/led.vwf
design_name = led
instance = comp, \Selector7~315_I\, Selector7~315, led, 1
instance = comp,
www.eeworm.com/read/484108/1271932
vo modelsim_test.vo
// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any o
www.eeworm.com/read/484107/1271936
xrf ufmtest_modelsim.xrf
vendor_name = ModelSim
source_file = 1, C:/franchiese/FPGA文档资料/altera设计实例/MAX II和MAX设计实例/UFTtest/para_ufm.qip
source_file = 1, C:/franchiese/FPGA文档资料/altera设计实例/MAX II和MAX设计实例/UFTtest/para_ufm.v
so
www.eeworm.com/read/484105/1271942
xrf myosctest_modelsim.xrf
vendor_name = ModelSim
source_file = 1, C:/franchiese/FPGA文档资料/altera设计实例/MAX II和MAX设计实例/an496_design_example/myosctest/myosctest.v
source_file = 1, C:/franchiese/FPGA文档资料/altera设计实例/MAX II和MAX设计实例/
www.eeworm.com/read/466574/1510284
_modelsim_work__info ._modelsim_work__info
m255
13
cModel Technology
dD:\altera\quartus50\decode\simulation\modelsim
T_opt
VML84n4H`XQ>jDaQlhRQlJ3
015 3 4 ./modelsim_work top fast 0
o-quiet -auto_acc_if_foreign -work work -L D:/altera/quartu