sram_modelsim.v

FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！

`timescale 1ns / 1ps
module sram_test(clk,
								 rst,
								 data1,
								 addr1,
								 ce1,
								 we1,
								 oe1,
								 data2,
								 addr2,
								 ce2,
								 we2,
								 oe2,
								 data_in,
								 data_in_en,
								 data_out);
//port  
	input clk,rst,data_in_en;
  input [7:0] data_in;
  output [7:0]  data_out;
  inout [7:0] data1,data2; 
 	output [17:0] addr1,addr2;
  output ce1,we1,oe1,ce2,we2,oe2;
//intra port 
	reg [7 :0] data_out;
  reg [17:0] addr1_reg,addr2_reg;
  wire [17:0] addr1,addr2;
  wire[7 :0] data1,data2;
  wire ce1,we1,oe1,ce2,we2,oe2;
  reg ram_sele;
  wire [7:0] data_reg;
  reg data_in_en_reg;//延时data_in_en_reg	
//设置写ram地址
always @ (posedge clk or negedge rst)
	begin
		if(!rst)
			begin
				ram_sele<=0;
			end
		else
			begin
				data_in_en_reg<=data_in_en;
				if(data_in_en)
					begin
						if(addr1_reg==8'd63)
							begin
								addr1_reg<=8'h0;
								ram_sele<=~ram_sele;
							end
						else
							addr1_reg<=addr1_reg+1;
					end
				else
					addr1_reg<=8'h0;
			end
	end
//设置读ram地址
always @ (posedge clk or negedge rst)
	begin
		if(!rst)
			begin
				ram_sele<=0;
			end
		else
			begin
				if(data_in_en)
					begin
						if(addr2_reg==8'd63)
							begin
								addr2_reg<=8'h0;
							end
						else
							addr2_reg<=addr2_reg+1;
					end
				else
					addr2_reg<=8'h0;
			end
	end	
//乒乓读写ram，ram_sele＝0,写的一片,读第二片;ram_sele＝1,写第二片,读第一片
	assign ce1=1'b0;
	assign ce2=1'b0;	
	assign we1=(!ram_sele&&data_in_en)?(~clk):
						 (!data_in_en)?1'b0:1'b1;
	assign oe1=( ram_sele&&data_in_en)?clk:1'b1;
	assign we2=( ram_sele&&data_in_en)?(~clk):
						 (!data_in_en)?1'b0:1'b1;
	assign oe2=(!ram_sele&&data_in_en)?clk:1'b1;
	assign addr1=(!ram_sele&&data_in_en)?addr1_reg:addr2_reg;
	assign addr2=(!ram_sele&&data_in_en)?addr2_reg:addr1_reg;
	assign data1=(!ram_sele&&data_in_en)?data_in:8'hzz;
	assign data2=( ram_sele&&data_in_en)?data_in:8'hzz;
	assign data_reg=(!ram_sele&&data_in_en)?data2:
									( ram_sele&&data_in_en)?data1:data_in;	
	always @ (posedge clk)
		begin
			data_out<=data_reg;
		end	             
endmodule
/////////////////////sram仿真模块/////////////////////////////////////
module sram(addr,data,we,oe,ce) ;
input[17:0]addr;
inout[7:0]data;
input we,oe,ce;
wire[7:0] data;
reg[7:0] mem[262143:0];
assign data=(!ce&&!oe&&we)?mem[addr]:8'hzz;
wire[7:0]temp=mem[addr];
always @(posedge we)
  mem[addr]<=data;
endmodule
//////////////////////test bench////////////////////////////////////////
module sram_modelsim_top;
//port
reg clk,rst,data_in_en;
reg [7:0] data_in;
wire [7:0]  data_out;
wire [7:0] data1,data2; 
wire [17:0] addr1,addr2;
wire ce1,we1,oe1,ce2,we2,oe2;
//intra port
reg [0 :8] mm [0:1670399];
reg [21:0] i;  
always #20 clk=~clk;
initial
begin
	clk=0;rst=1;
	#50 rst=0;
	#50 rst=1;
	$readmemh("E:/div.dat",mm);
end
always @ (posedge clk)
	if(!rst)
		begin
			i<=0;
		end
	else
		begin
			i<=i+1;
			{data_in_en,data_in}<=mm[i];
		end
sram_test sram_test(	
								 .clk       (clk),
								 .rst       (rst),
								 .data1     (data1),
								 .addr1     (addr1),
								 .ce1       (ce1),
								 .we1       (we1),
								 .oe1       (oe1),
								 .data2     (data2),
								 .addr2     (addr2),
								 .ce2       (ce2),
								 .we2       (we2),
								 .oe2       (oe2),
								 .data_in   (data_in),
								 .data_in_en(data_in_en),
								 .data_out  (data_out)
					);
sram sram1(
								 .data		(data1),
								 .addr		(addr1),
								 .ce  		(ce1  ),
								 .we  		(we1  ),
								 .oe  		(oe1  )
					);
sram sram2(                  
							 	.data			(data2), 
							 	.addr			(addr2), 
							 	.ce  			(ce2  ), 
							 	.we  			(we2  ), 
							  .oe  			(oe2  )  
					);    
endmodule