代码搜索：modelSim
找到约 1,834 项符合「modelSim」的源代码
代码结果 1,834
www.eeworm.com/read/219674/14870859
vstf vish_stacktrace.vstf
# Current time Fri Dec 15 09:35:25 2006
# ModelSim Stack Trace
# Program = vish
# Id = "6.0d"
# Version = "2005.04"
# Date = "Apr 26 2005"
# Platform = win32pe
Exception c0000005 has occurred
www.eeworm.com/read/214502/15098392
ldo song.ldo
# Auto generated by Project Navigator for Modelsim
vlib work
vlog song.v
vlog "D:/Xilinx/verilog/src/glbl.v"
## You need to generate your own stimuli
vsim -t 1ps +maxdelays -L xilinxcorelib_v
www.eeworm.com/read/18550/793442
ldo song.ldo
# Auto generated by Project Navigator for Modelsim
vlib work
vlog song.v
vlog "D:/Xilinx/verilog/src/glbl.v"
## You need to generate your own stimuli
vsim -t 1ps +maxdelays -L xilinxcorelib_v
www.eeworm.com/read/18563/794267
ldo alu.ldo
# Auto generated by Project Navigator for Modelsim
vlib work
vlog J:/eda/Xilinx/verilog/src/glbl.v
vlog -work work ALU.V
## You need to generate your own Verilog stimuli
vsim -t 1ps +maxdelay
www.eeworm.com/read/343627/3218948
ldo alu.ldo
# Auto generated by Project Navigator for Modelsim
vlib work
vlog J:/eda/Xilinx/verilog/src/glbl.v
vlog -work work ALU.V
## You need to generate your own Verilog stimuli
vsim -t 1ps +maxdelay
www.eeworm.com/read/154076/5643167
ldo alu.ldo
# Auto generated by Project Navigator for Modelsim
vlib work
vlog J:/eda/Xilinx/verilog/src/glbl.v
vlog -work work ALU.V
## You need to generate your own Verilog stimuli
vsim -t 1ps +maxdelay
www.eeworm.com/read/187841/8596524
do func_sim.do
# 16b/20b Functional Simulation ModelSim DO file
# Create work library
vlib work
# Compile package files
vcom -just e -93 -explicit -work work pkg_convert.vhd
vcom -skip e -93 -explicit -wo
www.eeworm.com/read/174927/9568290
transcript
# Reading C:/Modeltech_xe/tcl/vsim/pref.tcl
# do test.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
# --
www.eeworm.com/read/167055/9982922
mti fulladder.cr.mti
{F:/FPGA exp/FullAdder/top.vhd} {1 {vcom -work work -2002 -explicit {F:/FPGA exp/FullAdder/top.vhd}
Model Technology ModelSim SE vcom 6.1b Compiler 2005.09 Sep 8 2005
-- Loading package standard
-
www.eeworm.com/read/353400/10449744
mti romtest.cr.mti
D:/rom/rom.vhd {1 {vcom -work work -2002 -explicit D:/rom/rom.vhd
Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
-- Loading package standard
-- Loading package std_logic_1164
-