代码搜索：mdk arm
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www.eeworm.com/read/309608/13667846
arm makefile.arm
CC=arm-linux-gcc
CFLAGS = -D_FILE_OFFSET_BITS=64
OFLAGS = -O
OBJS= bignum.o rsa.o sha1.o
.SILENT:
all: static
static: libxyssl.a
libxyssl.a: $(OBJS)
echo " AR $@"
ar r $@ $(OBJS)
echo "
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arm makefile.arm
##############################
# CamDetect Makefile
##############################
CC=arm-linux-gcc
SERVFLAGS= -O2 -DLINUX $(WARNINGS)
SERVLIBS= -lpthread -Lxyssl -lxyssl
#WARNINGS = -Wall \
#
www.eeworm.com/read/308751/13693503
ndo arm.ndo
## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Verilog Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model for Module armtst
vlog "C:/Xilinx/verilo
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udo arm.udo
-- ProjNav VHDL simulation template: arm.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
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ant arm.ant
// E:\ISE6.1\TST
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Sun May 06 09:28:57 2007
`timescale 1ns/1ns
`define F_ASSERT 2
`define s3 3
`define N 5
`define IF1 2
`
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tfw arm.tfw
// E:\ISE6.1\TST
// Verilog Test fixture created by
// HDL Bencher 6.1i
// Sun May 06 09:28:57 2007
//
// Notes:
// 1) This test fixture has been automatically generated from
// your Test Be
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fdo arm.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sun May 06 09:28:58 中国标准时间 2007
##
vlib work
vlog my_dcm1.v
vlog rom.v
vlog armtst.v
vlog arm.tfw
vlog C:/Xi
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tbw arm.tbw
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scatter arm.scatter
LOAD_ROM 0x0000000
{
ER_INIT 0x0c00000
{
Init (+RO)
}
ER_ROM +0
{
.ANY(+RO)
}
DATABLACK
{
RamData (
www.eeworm.com/read/305275/13775942