代码搜索：maxII
找到约 205 项符合「maxII」的源代码
代码结果 205
www.eeworm.com/read/161013/5564364
tdf cntr_uv7.tdf
--lpm_counter DEVICE_FAMILY="MAX II" lpm_direction="UP" lpm_width=8 clk_en clock cnt_en q
--VERSION_BEGIN 4.1 cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compa
www.eeworm.com/read/161013/5564366
tdf cntr_hc7.tdf
--lpm_counter DEVICE_FAMILY="MAX II" lpm_direction="UP" lpm_width=20 clk_en clock q
--VERSION_BEGIN 4.1 cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_compare 200
www.eeworm.com/read/161013/5564367
tdf cntr_c18.tdf
--lpm_counter DEVICE_FAMILY="MAX II" lpm_direction="UP" lpm_width=24 clk_en clock cnt_en q
--VERSION_BEGIN 4.1 cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_lpm_add_sub 2004:06:23:12:24:04:SJ cbx_lpm_comp
www.eeworm.com/read/271017/11012775
eqn main.map.eqn
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
www.eeworm.com/read/217144/4876017
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity maxii_latch is
port(
D : in vl_logic;
ENA : in vl_logic;
PRE : in vl_log
www.eeworm.com/read/208358/4993587
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity maxii_latch is
port(
D : in vl_logic;
ENA : in vl_logic;
PRE : in vl_log
www.eeworm.com/read/268991/4247972
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity maxii_latch is
port(
D : in vl_logic;
ENA : in vl_logic;
PRE : in vl_log
www.eeworm.com/read/217144/4876021
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity maxii_dffe is
port(
Q : out vl_logic;
CLK : in vl_logic;
ENA : in vl_logi
www.eeworm.com/read/217144/4876030
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity maxii_mux21 is
port(
MO : out vl_logic;
A : in vl_logic;
B : in vl_log
www.eeworm.com/read/217144/4876031
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity maxii_nmux21 is
port(
MO : out vl_logic;
A : in vl_logic;
B : in vl_lo