代码搜索：interconnect
找到约 755 项符合「interconnect」的源代码
代码结果 755
www.eeworm.com/read/39119/1120107
blc system_axi_interconnect_1_wrapper.blc
Release 14.2 ngcbuild P.28xd (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Command Line: C:\Xilinx\14.2\ISE_DS\ISE\bin\nt\unwrapped\ngcbuild.exe -p
xc7z020clg484-1 -intstyle silent
www.eeworm.com/read/39119/1120126
ngc system_axi_interconnect_1_wrapper.ngc
www.eeworm.com/read/39119/1120133
ngc system_axi_interconnect_1_wrapper.ngc
www.eeworm.com/read/39119/1120153
ngc system_axi_interconnect_1_wrapper.ngc
www.eeworm.com/read/39119/1120157
ncf system_axi_interconnect_1_wrapper.ncf
INST "axi_interconnect_1/*clock_conv*/*_resync*" TNM = FFS "axi_interconnect_1_reset_resync";
TIMEGRP "axi_interconnect_1_reset_source" = FFS PADS CPUS;
TIMESPEC "TS_axi_interconnect_1_reset_resync"
www.eeworm.com/read/39119/1120676
lso system_axi_interconnect_1_wrapper.lso
axi_interconnect_v1_06_a
work
www.eeworm.com/read/39119/1120688
v system_axi_interconnect_1_wrapper.v
//-----------------------------------------------------------------------------
// system_axi_interconnect_1_wrapper.v
//-----------------------------------------------------------------------------
www.eeworm.com/read/226455/14465313
pdf rapid_io_interconnect_specification_physical_layer.pdf
www.eeworm.com/read/39099/913830
prj system_axi_interconnect_1_wrapper_xst.prj
verilog axi_interconnect_v1_06_a C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_06_a/hdl/verilog/ict106_axic_sample_cycle_ratio.v
verilog axi_interconnect_v1_06_a C:\Xil
www.eeworm.com/read/39099/913838
scr system_axi_interconnect_1_wrapper_xst.scr
set -tmpdir D:\_prj\Xilinx\Blog\Lab4\synthesis\xst_temp_dir\
run
-opt_mode speed
-netlist_hierarchy as_optimized
-opt_level 1
-p xc7z020clg484-1
-top system_axi_interconnect_1_wrapper
-ifmt MIX