system_axi_interconnect_1_wrapper.ncf

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

INST "axi_interconnect_1/*clock_conv*/*_resync*" TNM = FFS "axi_interconnect_1_reset_resync";
TIMEGRP "axi_interconnect_1_reset_source" = FFS PADS CPUS;
TIMESPEC "TS_axi_interconnect_1_reset_resync" = FROM "axi_interconnect_1_reset_source" TO "axi_interconnect_1_reset_resync" TIG;