代码搜索:instance

找到约 10,000 项符合「instance」的源代码

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www.eeworm.com/read/351665/10632221

qsf test.qsf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any
www.eeworm.com/read/159535/10642066

qsf pipemult_lc_phys_syn.qsf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any
www.eeworm.com/read/159535/10643611

qsf pipemult_lc.qsf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any
www.eeworm.com/read/275831/10794407

rb 09 - avoiding boilerplate code with metaprogramming.rb

class Fetcher def fetch(how_many) puts "Fetching #{how_many ? how_many : "all"}." end def fetch_one fetch(1) end def fetch_ten fetch(10) end def fetch_all fetch(nil)
www.eeworm.com/read/274751/10855186

xml mycpu.cbx.xml

www.eeworm.com/read/273824/10899912

c fuse_signals.c

/* FUSE: Filesystem in Userspace Copyright (C) 2001-2006 Miklos Szeredi This program can be distributed under the terms of the GNU LGPL. See the file COPYING.LIB
www.eeworm.com/read/416926/11009349

vhd fltr_compute_h2.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fltr_compute_h2 is port( clk: in std_logic; din : std_logic_vector(55 downto 0); d
www.eeworm.com/read/416926/11009404

vhd fltr_compute_f1.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fltr_compute_f1 is port( clk: in std_logic; din : std_logic_vector(55 downto 0); d
www.eeworm.com/read/416926/11009445

vhd fltr_compute_f2.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fltr_compute_f2 is port( clk: in std_logic; din : std_logic_vector(55 downto 0); d
www.eeworm.com/read/416926/11009502

vhd fltr_compute_h4.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity fltr_compute_h4 is port( clk: in std_logic; din : std_logic_vector(55 downto 0); d