代码搜索：initial
找到约 10,000 项符合「initial」的源代码
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www.eeworm.com/read/345113/11838247
bak st7637_uv2.bak
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (Target 1), 0x0000 // Tools: 'MCS-51'
Group (Source Group 1)
File 1,2, 0x0
File 1,1,
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uv2 st7637.uv2
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (Target 1), 0x0000 // Tools: 'MCS-51'
Group (Source Group 1)
File 1,2, 0x0
File 1,1,
www.eeworm.com/read/258646/11848229
v t_bin_cnt_part_rtl_by_3.v
module t_Binary_Counter_Partioned_RTL_by_3 ();
parameter size = 4;
wire [size -1: 0] count;
reg enable;
reg clk, rst;
Binary_Counter_Part_RTL_by_3 M0 (count, enable, clk, rst);
initi
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v bcd_to_excess_3b.v
module BCD_to_Excess_3b (B_out, B_in, clk, reset_b);
output B_out;
input B_in, clk, reset_b;
parameter S_0 = 3'b000, // State assignment
S_1 = 3'b001,
S_2 = 3'b101,
S_3 = 3'b1
www.eeworm.com/read/258643/11848434
v seq_rec_3_1s_moore.v
module Seq_Rec_3_1s_Moore (D_out, D_in, En, clk, reset);
output D_out;
input D_in, En;
input clk, reset;
parameter S_idle = 0; // One-Hot
parameter S_0 = 1;
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v test_count_ones_b.v
module t_count_ones_b ();
parameter data_width = 4;
parameter count_width = 3;
wire [count_width-1:0] bit_count_0, bit_count_1, bit_count_2;
reg [data_width-1:0] data;
www.eeworm.com/read/258643/11848444
v seq_rec_3_1s_mealy.v
module Seq_Rec_3_1s_Mealy (D_out, D_in, En, clk, reset);
output D_out;
input D_in, En;
input clk, reset;
parameter S_idle = 0; // Binary code
parameter S_0 = 1;
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v test_nrz_2_manchester_moore.v
`timescale 1 ns / 10 ps
module test_NRZ_2_Manchester_Moore ();
reg B_in, reset_b;
wire B_out, clock;
NRZ_2_Manchester_Moore M1 (B_out, B_in, clock_2, reset_b);
Clock_1_2 M2 (clock_1, clock_2);
www.eeworm.com/read/258643/11848796
v bcd_to_excess_3c.v
module BCD_to_Excess_3c (B_out, B_in, clk, reset_b);
output B_out;
input B_in, clk, reset_b;
parameter S_0 = 3'b000, // State assignment
S_1 = 3'b001,
S_2 = 3'b101,
S_3 = 3'b1
www.eeworm.com/read/258642/11848855
v t_bin_cnt_part_rtl.v
module t_Binary_Counter_Partioned_RTL ();
parameter size = 4;
wire [size -1: 0] count;
reg enable;
reg clk, rst;
Binary_Counter_Part_RTL M0 (count, enable, clk, rst);
initial #300 $f