代码搜索:initial

找到约 10,000 项符合「initial」的源代码

代码结果 10,000
www.eeworm.com/read/326423/13142933

v funct_tp.v

`define clk_cycle 50 `include "funct.v" module funct_tp; reg[3:0] n; reg reset,clk; wire[31:0] result; initial begin n=0; reset=1; clk=0; for(n=0;n
www.eeworm.com/read/326356/13145453

v crc16_d8_m_tb.v

module crc16_d8_m_tb; reg [7:0] data; reg clk; reg rst_n; reg d_valid; wire [15:0] crc_data; initial clk = 1'b0; always #5 clk
www.eeworm.com/read/326116/13165266

v funct_tp.v

`define clk_cycle 50 `include "funct.v" module funct_tp; reg[3:0] n; reg reset,clk; wire[31:0] result; initial begin n=0; reset=1; clk=0; for(n=0;n
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h tm_extr.h

/*************************************************************************/ /* */ /* Copyright (c) 1993-1998 Accelerated
www.eeworm.com/read/240985/13181986

cpp emp4_18.cpp

// emp4_18 #include "linklist.h" void visitehsllist(link l) { link p; p=l->next; while (p!=NULL){ visite_snode(p,1); p=p->next; } } void main() { link l; initial_
www.eeworm.com/read/240617/13210963

lst hardware.lst

Sunplus u'nSP Assembler - Ver. 1.8.0 //======================================================================================== // Progarm
www.eeworm.com/read/324473/13261642

v funct_tp.v

`define clk_cycle 50 `include "funct.v" module funct_tp; reg[3:0] n; reg reset,clk; wire[31:0] result; initial begin n=0; reset=1; clk=0; for(n=0;n
www.eeworm.com/read/324454/13262436

v dpll_xor_tp.v

module DPLL_xor_tp; reg fin,fout; wire se; parameter dely=100; DPLL_xor inst_DPLL_xor(fin,fout,se); initial begin fin=0;fout=0; #(dely*10) fout=1; #(dely*10) fout=0; #(dely*10) $stop; end always
www.eeworm.com/read/324454/13262494

txt dpll_xor_tp.txt

module DPLL_xor_tp; reg fin,fout; wire se; parameter dely=100; DPLL_xor inst_DPLL_xor(fin,fout,se); initial begin fin=0;fout=0; #(dely*10) fout=1; #(dely*10) fout=0; #(dely*10) $stop;
www.eeworm.com/read/324454/13262548

v dpll_h_tp.v

module DPLL_H_tp; reg kclock,reset; reg[7:0] H; wire idclock; parameter dely=100; DPLL_H inst_DPLL_H(idclock,kclock,H,reset); initial begin kclock=1;H=2;reset=0; #(dely*20) reset=1; #(dely*20) H=3;