crc16_d8_m_tb.v

来自「crc_table.c is for reset seed( 0000 ) c」· Verilog 代码 · 共 35 行

module crc16_d8_m_tb;
    
    reg [7:0] data;
    reg clk;
    reg rst_n;
    reg d_valid;
    wire [15:0] crc_data;
    
    initial clk = 1'b0;
    
    always #5 clk <= ~clk;
    
    initial begin
        rst_n = 1'b0;
        d_valid = 1'b0;
        #200 rst_n = 1'b1;
        #100 d_valid = 1'b1;
    end
    
    always @(posedge clk)
    begin
        if(~rst_n)
        data <= 8'b0;
        else
        data <= 8'b1;
    end
    
    CRC16_D8  U_CRC16_D8( .clk    (clk),
                          .rst_n  (rst_n),
                          .d_valid(d_valid),
                          .D   (data),
                          .C (crc_data));
                          
                          
endmodule