代码搜索：initial
找到约 10,000 项符合「initial」的源代码
代码结果 10,000
www.eeworm.com/read/173458/9656986
cpp ctevent.cpp
#include "ctevent.h"
#include
event_mutex::event_mutex(char *MName, BOOL Initial, unsigned long Dur)
{
strcpy(MutexName,MName);
EventMutex = CreateEvent(NULL,FALSE, Init
www.eeworm.com/read/368994/9669607
txt 新建 文本文档.txt
% SIXDOFVM Calculate aircraft variable-mass rigid-body six-degrees-of-freedom
% equations of motion using MATLAB ODE45 solver.
%
% =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
% Inputs:
% =-=-=-=
www.eeworm.com/read/368990/9669641
txt 新建 文本文档.txt
% SIXDOF Calculate aircraft fixed-mass rigid-body six-degrees-of-freedom
% equations of motion using MATLAB ODE45 solver.
%
% =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
% Inputs:
% =-=-=-=-=-=-
www.eeworm.com/read/172784/9690445
v my_strobe_test.v
/**********************************************************************
* $my_strobe example -- Verilog test bench source code
*
* Verilog test bench to test the $my_strobe PLI application.
*
www.eeworm.com/read/172784/9690449
v my_monitor1_test.v
/**********************************************************************
* $my_monitor1 example -- Verilog test bench source code
*
* Verilog test bench to test the $my_monitor1 PLI application.
www.eeworm.com/read/172784/9690460
v my_monitor2_test.v
/**********************************************************************
* $my_monitor2 example -- Verilog test bench source code
*
* Verilog test bench to test the $my_monitor1 PLI application.
www.eeworm.com/read/368409/9697009
tf sevenseg_case_tb.tf
module testbench();
// Inputs
reg [3:0] hex;
// Outputs
wire [7:0] seg;
// Instantiate the UUT
sevenseg_case uut (
.hex(hex),
.seg(seg)
);
www.eeworm.com/read/368409/9697020
tf reg4_nbp_tb.tf
module testbench();
// DATE: Thu May 01 10:38:03 2003
// TITLE:
// MODULE: reg4_bpa
// DESIGN: reg4_bpa
// FILENAME: reg4_bpa
// PROJECT: reg4
// VERSION: Version 1.0
www.eeworm.com/read/368409/9697038
tf reg4_bpa_tb.tf
module testbench();
// DATE: Thu May 01 10:38:03 2003
// TITLE:
// MODULE: reg4_bpa
// DESIGN: reg4_bpa
// FILENAME: reg4_bpa
// PROJECT: reg4
// VERSION: Version 1.0
www.eeworm.com/read/172624/9699787
bak lpm_multtest.v.bak
`timescale 1ns/1ns
module lpm_multest;
reg [7:0]dataa,datab,sum;
reg clock,clken,aclr;
wire[15:0] result;
parameter dely=25;
lpm_mult lpm_mult ( result, dataa, datab, sum, clock, clken, aclr ) ;
ini