代码搜索：initial
找到约 10,000 项符合「initial」的源代码
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www.eeworm.com/read/255510/12077972
v random_tp.v
`timescale 10ns/1ns
module random_tp;
integer data;
integer i;
parameter delay=10;
initial $monitor($time,,,"data=%b",data);
initial
begin
for(i=0; i
www.eeworm.com/read/255510/12077996
v time_dif.v
`timescale 10ns/1ns
module time_dif;
reg ts;
parameter delay=2.6;
initial
begin
#delay ts=1;
#delay ts=0;
#delay ts=1;
#delay ts=0;
end
initial $monitor($time,,,"
www.eeworm.com/read/255510/12077997
v mult_tp.v
`timescale 10ns/1ns
module mult_tp;
reg[7:0] a,b;
wire [15:0] out;
integer i,j;
mult8 m1(out,a,b);
initial
begin
a=0;b=0;
for(i=1;i
www.eeworm.com/read/341489/12082269
h system.h
extern int System_Initial();
extern int SP_INT_IRQ5();
extern int System_ServiceLoop();
www.eeworm.com/read/341420/12084648
c table.c
// table.c
/********************************************************************/
/* */
/* Initial Memory data table
www.eeworm.com/read/255244/12093464
bak general_opt.bak
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.s*; *.src; *.a*)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt; *.h; *.inc)
pExt (*.plm)
CppX (*.cpp)
DaveTm {
www.eeworm.com/read/254980/12110143
v tcounter.v
// download from: www.pld.com.cn & www.fpga.com.cn
module test_counter;
reg clk, rst;
wire [7:0] count;
counter #(5,10) dut (count,clk,rst);
initial // Clock generator
begin
cl
www.eeworm.com/read/152386/12118382
txt 测试向量（test bench）和波形发生器：verilog hdl 程序举例---相应加法器的测试向量（test bench).txt
module test_counter;
reg clk, rst;
wire [7:0] count;
counter #(5,10) dut (count,clk,rst);
initial // Clock generator
begin
clk = 0;
#10 forever #10 clk = !clk;
end
in
www.eeworm.com/read/340943/12119731
lst cs16-1.lst
C51 COMPILER V7.06 CS16_1 02/11/2007 09:55:28 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE CS16_1
OBJECT MODULE PLACED IN