测试向量（test bench）和波形发生器：verilog hdl 程序举例---相应加法器的测试向量（test bench).txt

vhdl 测试向量含测试向量（Test Bench）和波形产生：VHDL实例---相应加法器的测试向量（test bench).txt

module test_counter;
 
reg clk, rst;
wire [7:0] count;
 
counter #(5,10) dut (count,clk,rst);
 
initial // Clock generator
  begin
    clk = 0;
    #10 forever #10 clk = !clk;
  end
  
initial   // Test stimulus
  begin
    rst = 0;
    #5 rst = 1;
    #4 rst = 0;
    #50000 $stop;
  end
  
initial
    $monitor($stime,, rst,, clk,,, count); 
    
endmodule