代码搜索:initial

找到约 10,000 项符合「initial」的源代码

代码结果 10,000
www.eeworm.com/read/460441/7249932

ctl userctl1.ctl

VERSION 5.00 Begin VB.UserControl GurhanCoolButton AutoRedraw = -1 'True ClientHeight = 1470 ClientLeft = 0 ClientTop = 0 ClientWidth = 4080
www.eeworm.com/read/460207/7255736

bak parity_check.v.bak

module Parity_Check; reg [0:7] a; reg s; initial begin a=8'b11000111; end function Parity; input [0:7] Set; //output Parity; //reg Parity; reg[0:2] Ret; integer j; begi
www.eeworm.com/read/460207/7255744

v parity_check.v

module Parity_Check; reg [0:7] a; reg s; initial begin a=8'b11000111; end function Parity; input [0:7] Set; //output Parity; //reg Parity; reg[0:2] Ret; integer j; begi
www.eeworm.com/read/460207/7255763

v test.v

module Test; reg clock,updn; wire[0:3]cnt_out; countupdown c1(clock,cnt_out,updn); always #1 clock=~clock; initial begin clock=0; updn=0; #50 updn=1; #100 $dumpflush; $stop; end ini
www.eeworm.com/read/460207/7255788

bak test.v.bak

module Test; reg clock,updn; wire[0:3]cnt_out; countupdown c1(clock,cnt_out,updn); always #1 clock=~clock; initial begin updn=0; #50 updn=1; #100 $dumpflush; $stop; end initial begin
www.eeworm.com/read/458490/7295837

v labtest.v

// Verilog Test Fixture Template `timescale 1 ns / 1 ps module TEST_gate; // The following code initializes the Global Set Reset (GSR) and Global Three-State (GTS) nets // Refe
www.eeworm.com/read/458490/7295908

v labtest1.v

// Verilog Test Fixture Template `timescale 1 ns / 1 ps module TEST_gate; // The following code initializes the Global Set Reset (GSR) and Global Three-State (GTS) nets // Refe
www.eeworm.com/read/457112/7334092

lst main.lst

C51 COMPILER V8.02 MAIN 12/10/2008 22:55:07 PAGE 1 C51 COMPILER V8.02, COMPILATION OF MODULE MAIN OBJECT MODULE PLACED IN ma
www.eeworm.com/read/456603/7343879

v random_tp.v

`timescale 10ns/1ns module random_tp; integer data; integer i; parameter delay=10; initial $monitor($time,,,"data=%b",data); initial begin for(i=0; i
www.eeworm.com/read/456603/7343892

v time_dif.v

`timescale 10ns/1ns module time_dif; reg ts; parameter delay=2.6; initial begin #delay ts=1; #delay ts=0; #delay ts=1; #delay ts=0; end initial $monitor($time,,,"