parity_check.v.bak

来自「FPGA的集成开发环境ISE中课仿真的Verilog代码集锦」· BAK 代码 · 共 32 行

module Parity_Check;
reg [0:7] a;

reg s;
initial begin
 a=8'b11000111;
 end
function Parity;
    input [0:7] Set;
    //output Parity;
    //reg Parity;
    reg[0:2] Ret;
    integer j;
    
    begin
       Ret=0;
       for(j=0;j<8;j=j+1)begin
         if(Set[j]==1)
         Ret=Ret+1;  
       end 
      Parity=Ret%2;
    end
endfunction

initial begin
   Parity(a,s);
   $display("a=%b,s=%b",a,s);
end  
endmodule