代码搜索：fpga

找到约 10,000 项符合「fpga」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/450040/7491303

v ad7301_ctrl.v

module ad7301_ctrl(reset, LCLK, sample_start, SCLK,//shu chu ad xin pian dang zhong DOUT,//cong ad xin pian zhong hui du,shu ru dao FPGA zhong //ad7301_CS_,//shu ch
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www.eeworm.com/read/448593/7529108

txt 带同步复位的状态机.txt

-- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity stmch1 is port(clk, in1, rst: in std_logic;
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www.eeworm.com/read/448304/7535318

c com.c

// RS-232 example // Compiles with Microsoft Visual C++ 5.0/6.0 // (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006 #include #include #include HANDLE hCom;
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www.eeworm.com/read/444020/7619307

txt spi_verilog_mycode.txt

// sync SCK to the FPGA clock using a 3-bits shift register reg [2:0] SCKr; always @(posedge clk) SCKr
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www.eeworm.com/read/199789/7822526

txt 移位寄存器：74164.txt

-- TTL164 Shift Register -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY dev164 IS PORT(a, b, nclr, clock : IN BIT; q : BUFFE
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www.eeworm.com/read/199789/7822613

txt 经典双进程状态机（含test beach）.txt

-- Classic 2-Process State Machine and Test Bench -- MEALY TYPE STATE MACHINE EXAMPLE -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; ENTITY fsm I
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www.eeworm.com/read/199789/7822621

txt 带同步复位的状态机.txt

-- State Machine with Asynchronous Reset -- dowload from: www.fpga.com.cn & www.pld.com.cn library ieee; use ieee.std_logic_1164.all; entity stmch1 is port(clk, in1, rst: in std_logic;
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www.eeworm.com/read/199789/7822653

txt 双2－4译码器：74139.txt

-- Dual 2-to-4 Decoder -- A set of conditional signal assignments model a dual 2-to-4 decoder -- uses 1993 std VHDL -- download from: www.pld.com.cn & www.fpga.com.cn library IEEE; use IEEE.Std
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www.eeworm.com/read/199789/7822656

txt 带三态输出的8位d寄存器：74374.txt

-- Octal D-Type Register with 3-State Outputs -- Simple model of an Octal D-type register with three-state outputs using two concurrent statements. -- download from: www.fpga.com.cn & www.pld.com.cn
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www.eeworm.com/read/198238/7946229

txt 位寄存器：74164.txt

-- TTL164 Shift Register -- download from: www.fpga.com.cn & www.pld.com.cn library IEEE; use IEEE.Std_logic_1164.all; ENTITY dev164 IS PORT(a, b, nclr, clock : IN BIT; q : BUFFE
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