ad7301_ctrl.v

多功能卡的源代码

module ad7301_ctrl(reset,
				        LCLK,
						sample_start,
						SCLK,//shu chu ad xin pian dang zhong
						DOUT,//cong ad xin pian zhong hui du,shu ru dao FPGA zhong
						//ad7301_CS_,//shu chu ad xin pian dang zhong
						ad7301_data,//shu chu dao FIFO zhong
						fifo_write,
						//channel_cs,//tong dao xuan ze shu chu ,wai jie 138_coder
						channel,
						DIN,
						ad7301_data_buf,
						SLOW_CLK
);
input reset;              //0 is the bit of reset
input LCLK;
input sample_start;
input DOUT;
output DIN;
output SCLK;
output [15:0] ad7301_data;
output fifo_write;
//output [7:0] channel_cs;
output [2:0] channel; 
output [15:0] ad7301_data_buf;
output SLOW_CLK;
wire DIN;
wire SCLK;
parameter [9:0] num1 = 10'd450;
parameter [9:0] num2 = 10'd900;
reg [9:0] counter;
reg SLOW_CLK;

always @(posedge LCLK or negedge reset)begin
		if(!reset) begin
			SLOW_CLK <= 1'b0;
			counter <= 10'd0;
			end
		else 
		begin
			if(counter<num2)	
			begin
				counter<=counter+10'd1;
				if (counter==num1)	SLOW_CLK<=1'b1;
			end		
			else	
			begin 
				SLOW_CLK<=1'b0;   
				counter<=10'd1;
			end		   		
			/*
			if (counter==(num1-1))   
			begin
				SLOW_CLK<=1'b1;
			end
			else if(counter==(num2-1))   
			begin 
			   SLOW_CLK<=1'b0;   
			   counter<=10'b0;
			end*/
			/*if(counter < num1)begin
				SLOW_CLK <= 1'b0;
				counter <= counter + 10'd1;
			end
			else if (counter < num2)begin
				SLOW_CLK <= 1'b1;
				counter <= counter + 10'd1;
			end
			else begin
				counter <= 10'd0;
			end*/
		end
end
wire  [15:0] ad7301_data;
wire fifo_write;
//wire  [7:0] channel_cs;
wire  [2:0] channel;
wire  [15:0] ad7301_data_buf;

ad7301_subctrl ad7301_subctrl(
		.reset(reset),
		.SLOW_CLK(SLOW_CLK),
		.sample_start(sample_start),
		.SCLK(SCLK),
		.DOUT(DOUT),
		.ad7301_data(ad7301_data),
		.fifo_write(fifo_write),
		//.channel_cs(channel_cs),
		.channel(channel),
		.DIN(DIN),
		.ad7301_data_buf(ad7301_data_buf)
);
endmodule