代码搜索：fpga
找到约 10,000 项符合「fpga」的源代码
代码结果 10,000
www.eeworm.com/read/415351/11075435
txt 多路选择器（使用when－else语句）.txt
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
www.eeworm.com/read/415351/11075456
txt 多路选择器（使用when－else语句）.txt
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
www.eeworm.com/read/415351/11075509
txt 三态总线（注2）.txt
VHDL:Tri-State Buses
download from: http://www.fpga.com.cn
prebus.vhd
LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY prebus IS
PORT(
my_in : IN STD_LOGIC_VECTOR(7 D
www.eeworm.com/read/415351/11075583
txt 三态总线（注2）.txt
VHDL:Tri-State Buses
download from: http://www.fpga.com.cn
prebus.vhd
LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY prebus IS
PORT(
my_in : IN STD_LOGIC_VECTOR(7 D
www.eeworm.com/read/268989/11112312
v 相应加法器的测试向量（test bench).v
// download from: www.pld.com.cn & www.fpga.com.cn
module test_counter;
reg clk, rst;
wire [7:0] count;
counter #(5,10) dut (count,clk,rst);
initial // Clock generator
begin
cl
www.eeworm.com/read/268989/11112314
v 12位寄存器.v
// User-Defined Macrofunction
// download from: http://www.fpga.com.cn
module reg12 ( d, clk, q);
input [11:0]d;
input clk;
output [11:0]q;
reg [11:0]q;
always @(posedge clk)
www.eeworm.com/read/411923/11222291
rpt test_createspi.rpt
Project Information d:\program\fpga\led driver\test_createspi.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 02/13/2009 16:11:50
Copyright (C) 1988-2002 Al
www.eeworm.com/read/205026/15329209
tdf altsyncram_dcq.tdf
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" INIT_FILE="e:\ywh\maxplus\fpga\sinwavegenerator\sin512.mif" NUMWORDS_A=512 OPERATION_MODE="ROM" OUTDATA
www.eeworm.com/read/205026/15329335
tdf altsyncram_dcq.tdf
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" INIT_FILE="e:\ywh\maxplus\fpga\sinwavegenerator\sin512.mif" NUMWORDS_A=512 OPERATION_MODE="ROM" OUTDATA
www.eeworm.com/read/356981/10218180
mht dm9000a原理及其与基带信号处理平台的结合应用,sdr,dm9000a,fpga,以太网-中电网.mht
From:
Subject: =?gb2312?B?RE05MDAwQdStwO28sMbk0+u7+bT40MW6xbSmwO3GvcyotcS94brP06bTwyw=?=
=?gb2312?B?U0RSLERNOTAwMEEsRlBHQSzS1Myrzfgt1tC15834?=
Date: Tue, 26 Au