代码搜索：fpga
找到约 10,000 项符合「fpga」的源代码
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www.eeworm.com/read/318858/3561707
cmd_log comparator.cmd_log
xst -intstyle ise -ifn __projnav/comparator.xst -ofn comparator.syr
ngdbuild -intstyle ise -dd f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic1\examples\comparator\ise\comparator/_ngo -i -p xc
www.eeworm.com/read/373367/2763033
sh sounder_tb.sh
#!/bin/sh
iverilog -y ../lib/ -y ../../../../usrp/fpga/sdr_lib \
sounder_tb.v -o sounder_tb && \
./sounder_tb > sounder_tb.out && \
grep 'r=0' sounder_tb.out | grep 'c=1' >
www.eeworm.com/read/360007/2970893
h memregions_4mib.h
/*
* Copyright (C) 2003-2005 Atmark Techno, Inc. All Rights Reserved.
*/
#ifndef _HERMIT_SUZAKU_MEMREGIONS_4MiB_H
#define _HERMIT_SUZAKU_MEMREGIONS_4MiB_H
#define FLASH_4MiB_FPGA_START (
www.eeworm.com/read/351582/3106525
vhd ps2.vhd
-- The FPGA-evb-S2 Xilinx Spartan-II evaluation board example
-- This example reads scan codes from a PS/2 keyboard and
-- displays them on LEDs.
-- (C)2001 Jan Pech, j.pech@sh.cvut.cz
library IEE
www.eeworm.com/read/198746/6786450
tfw mvbc3tbw.tfw
// D:\2006\FPGA_DESIGN\MVBC3\MVBC3
// Verilog Test fixture created by
// HDL Bencher 6.1i
// Wed Jan 10 21:08:37 2007
//
// Notes:
// 1) This test fixture has been automatically generated from
www.eeworm.com/read/174396/6790004
bak alteran.src.bak
# Altera Max+plus, EMax, Quartus and FPGA license file
FEATURE altera_fpgaexpress alterad 3000.0 permanent uncounted 0 HOSTID=e253ece41d80 ck=0
FEATURE altera_mainwin alterad 3000.0 permanent unco
www.eeworm.com/read/395324/8185518
txt 多路选择器.txt
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
www.eeworm.com/read/370579/9595027
txt 多路选择器（使用when－else语句）.txt
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
www.eeworm.com/read/370579/9595073
txt 计数器：generic语句的应用.txt
-- n-Bit Synchronous Counter
-- dowload from: www.fpga.com.cn & www.pld.com.cn
LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;
ENTITY cntrnbit IS
GENERIC(
www.eeworm.com/read/370579/9595095
txt 三态总线（注2）.txt
VHDL:Tri-State Buses
download from: http://www.fpga.com.cn
prebus.vhd
LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY prebus IS
PORT(
my_in : IN STD_LOGIC_VECTOR(7 D