mvbc3tbw.tfw

MVBC VHDL代码．．实现多功能车辆总线的通信

// D:\2006\FPGA_DESIGN\MVBC3\MVBC3
// Verilog Test fixture created by
// HDL Bencher 6.1i
// Wed Jan 10 21:08:37 2007
// 
// Notes:
// 1) This test fixture has been automatically generated from
//   your Test Bench Waveform
// 2) To use this as a user modifiable test fixture do the following:
//   - Save it as a file with a .tf extension (i.e. File->Save As...)
//   - Add it to your project as a testbench source (i.e. Project->Add Source...)
// 

`timescale 1ns/1ns

module mvbc3tbw;
	reg clk;
	reg rst;
	reg cs_cpu_n;
	reg int_mvbc0_n;
	reg int_mvbc1_n;
	reg wr_cpu_n;
	reg oe_cpu_n;
	reg [23:0] addr_cpu;
	reg rdy2mvbc_n;
	reg [6:0] CS;
	wire [23:0] addr_mvbc;
	wire rdy2cpu_n;
	wire rst_mvbc;
	wire wr_mvbc_n;
	wire rd_mvbc_n;
	wire cs_mvbc_n;
	wire int_cpu0_n;
	wire int_cpu1_n;
	wire JTEG_EN;
	wire SPARE0;

	mvbif UUT (
		.clk(clk),
		.rst(rst),
		.cs_cpu_n(cs_cpu_n),
		.int_mvbc0_n(int_mvbc0_n),
		.int_mvbc1_n(int_mvbc1_n),
		.wr_cpu_n(wr_cpu_n),
		.oe_cpu_n(oe_cpu_n),
		.addr_cpu(addr_cpu),
		.rdy2mvbc_n(rdy2mvbc_n),
		.CS(CS),
		.addr_mvbc(addr_mvbc),
		.rdy2cpu_n(rdy2cpu_n),
		.rst_mvbc(rst_mvbc),
		.wr_mvbc_n(wr_mvbc_n),
		.rd_mvbc_n(rd_mvbc_n),
		.cs_mvbc_n(cs_mvbc_n),
		.int_cpu0_n(int_cpu0_n),
		.int_cpu1_n(int_cpu1_n),
		.JTEG_EN(JTEG_EN),
		.SPARE0(SPARE0)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	clk = 1'b0;
	#5
	clk = 1'b1;
	#5
	#5
	clk = 1'b0;
	#5
	clk = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("results.txt");

	// --------------------
	rst = 1'b0;
	cs_cpu_n = 1'b1;
	int_mvbc0_n = 1'b0;
	int_mvbc1_n = 1'b0;
	wr_cpu_n = 1'b0;
	oe_cpu_n = 1'b0;
	addr_cpu = 24'b000000000000000000000000; //0
	rdy2mvbc_n = 1'b0;
	CS = 7'b0000000; //0
	// --------------------
	#20 // Time=20 ns
	rst = 1'b1;
	cs_cpu_n = 1'b1;
	// --------------------
	#20 // Time=40 ns
	cs_cpu_n = 1'b1;
	// --------------------
	#20 // Time=60 ns
	cs_cpu_n = 1'b1;
	rdy2mvbc_n = 1'b0;
	// --------------------
	#20 // Time=80 ns
	cs_cpu_n = 1'b0;
	// --------------------
	#60 // Time=140 ns
	cs_cpu_n = 1'b0;
	// --------------------
	#120 // Time=260 ns
	cs_cpu_n = 1'b1;
	// --------------------
	#40 // Time=300 ns
	cs_cpu_n = 1'b1;
	// --------------------
	#20 // Time=320 ns
	rdy2mvbc_n = 1'b0;
	// --------------------
	#60 // Time=380 ns
	rst = 1'b1;
	// --------------------
	#100 // Time=480 ns
	rdy2mvbc_n = 1'b0;
	// --------------------
	#40 // Time=520 ns
	cs_cpu_n = 1'b0;
	// --------------------
	#60 // Time=580 ns
	cs_cpu_n = 1'b1;
	// --------------------
	#140 // Time=720 ns
	rst = 1'b1;
	// --------------------
	#20 // Time=740 ns
	rst = 1'b1;
	// --------------------
	#20 // Time=760 ns
	cs_cpu_n = 1'b0;
	// --------------------
	#420 // Time=1180 ns
	cs_cpu_n = 1'b1;
	// --------------------
	#390 // Time=1570 ns
	// --------------------

	if (TX_ERROR == 0) begin
		$display("No errors or warnings");
		$fdisplay(TX_FILE,"No errors or warnings");
	end else begin
		$display("%d errors found in simulation",TX_ERROR);
		$fdisplay(TX_FILE,"%d errors found in simulation",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task CHECK_addr_mvbc;
	input [23:0] NEXT_addr_mvbc;

	#0 begin
		if (NEXT_addr_mvbc !== addr_mvbc) begin
			$display("Error at time=%dns addr_mvbc=%b, expected=%b",
				$time, addr_mvbc, NEXT_addr_mvbc);
			$fdisplay(TX_FILE,"Error at time=%dns addr_mvbc=%b, expected=%b",
				$time, addr_mvbc, NEXT_addr_mvbc);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_rdy2cpu_n;
	input NEXT_rdy2cpu_n;

	#0 begin
		if (NEXT_rdy2cpu_n !== rdy2cpu_n) begin
			$display("Error at time=%dns rdy2cpu_n=%b, expected=%b",
				$time, rdy2cpu_n, NEXT_rdy2cpu_n);
			$fdisplay(TX_FILE,"Error at time=%dns rdy2cpu_n=%b, expected=%b",
				$time, rdy2cpu_n, NEXT_rdy2cpu_n);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_rst_mvbc;
	input NEXT_rst_mvbc;

	#0 begin
		if (NEXT_rst_mvbc !== rst_mvbc) begin
			$display("Error at time=%dns rst_mvbc=%b, expected=%b",
				$time, rst_mvbc, NEXT_rst_mvbc);
			$fdisplay(TX_FILE,"Error at time=%dns rst_mvbc=%b, expected=%b",
				$time, rst_mvbc, NEXT_rst_mvbc);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_wr_mvbc_n;
	input NEXT_wr_mvbc_n;

	#0 begin
		if (NEXT_wr_mvbc_n !== wr_mvbc_n) begin
			$display("Error at time=%dns wr_mvbc_n=%b, expected=%b",
				$time, wr_mvbc_n, NEXT_wr_mvbc_n);
			$fdisplay(TX_FILE,"Error at time=%dns wr_mvbc_n=%b, expected=%b",
				$time, wr_mvbc_n, NEXT_wr_mvbc_n);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_rd_mvbc_n;
	input NEXT_rd_mvbc_n;

	#0 begin
		if (NEXT_rd_mvbc_n !== rd_mvbc_n) begin
			$display("Error at time=%dns rd_mvbc_n=%b, expected=%b",
				$time, rd_mvbc_n, NEXT_rd_mvbc_n);
			$fdisplay(TX_FILE,"Error at time=%dns rd_mvbc_n=%b, expected=%b",
				$time, rd_mvbc_n, NEXT_rd_mvbc_n);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_cs_mvbc_n;
	input NEXT_cs_mvbc_n;

	#0 begin
		if (NEXT_cs_mvbc_n !== cs_mvbc_n) begin
			$display("Error at time=%dns cs_mvbc_n=%b, expected=%b",
				$time, cs_mvbc_n, NEXT_cs_mvbc_n);
			$fdisplay(TX_FILE,"Error at time=%dns cs_mvbc_n=%b, expected=%b",
				$time, cs_mvbc_n, NEXT_cs_mvbc_n);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_int_cpu0_n;
	input NEXT_int_cpu0_n;

	#0 begin
		if (NEXT_int_cpu0_n !== int_cpu0_n) begin
			$display("Error at time=%dns int_cpu0_n=%b, expected=%b",
				$time, int_cpu0_n, NEXT_int_cpu0_n);
			$fdisplay(TX_FILE,"Error at time=%dns int_cpu0_n=%b, expected=%b",
				$time, int_cpu0_n, NEXT_int_cpu0_n);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_int_cpu1_n;
	input NEXT_int_cpu1_n;

	#0 begin
		if (NEXT_int_cpu1_n !== int_cpu1_n) begin
			$display("Error at time=%dns int_cpu1_n=%b, expected=%b",
				$time, int_cpu1_n, NEXT_int_cpu1_n);
			$fdisplay(TX_FILE,"Error at time=%dns int_cpu1_n=%b, expected=%b",
				$time, int_cpu1_n, NEXT_int_cpu1_n);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_JTEG_EN;
	input NEXT_JTEG_EN;

	#0 begin
		if (NEXT_JTEG_EN !== JTEG_EN) begin
			$display("Error at time=%dns JTEG_EN=%b, expected=%b",
				$time, JTEG_EN, NEXT_JTEG_EN);
			$fdisplay(TX_FILE,"Error at time=%dns JTEG_EN=%b, expected=%b",
				$time, JTEG_EN, NEXT_JTEG_EN);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_SPARE0;
	input NEXT_SPARE0;

	#0 begin
		if (NEXT_SPARE0 !== SPARE0) begin
			$display("Error at time=%dns SPARE0=%b, expected=%b",
				$time, SPARE0, NEXT_SPARE0);
			$fdisplay(TX_FILE,"Error at time=%dns SPARE0=%b, expected=%b",
				$time, SPARE0, NEXT_SPARE0);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

endmodule