代码搜索：fpga
找到约 10,000 项符合「fpga」的源代码
代码结果 10,000
www.eeworm.com/read/382666/6286475
txt 多路选择器（使用when－else语句）.txt
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
www.eeworm.com/read/382666/6286499
txt 三态总线（注2）.txt
VHDL:Tri-State Buses
download from: http://www.fpga.com.cn
prebus.vhd
LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY prebus IS
PORT(
my_in : IN STD_LOGIC_VECTOR(7 D
www.eeworm.com/read/494695/6360536
txt 多路选择器（使用when－else语句）.txt
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
www.eeworm.com/read/494695/6360560
txt 三态总线（注2）.txt
VHDL:Tri-State Buses
download from: http://www.fpga.com.cn
prebus.vhd
LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY prebus IS
PORT(
my_in : IN STD_LOGIC_VECTOR(7 D
www.eeworm.com/read/489686/6468778
v tcounter.v
// download from: www.pld.com.cn & www.fpga.com.cn
module test_counter;
reg clk, rst;
wire [7:0] count;
counter #(5,10) dut (count,clk,rst);
initial // Clock generator
begin
cl
www.eeworm.com/read/489686/6468780
v ram256x8_altera.v
// MAX+plus II Verilog Example
// LPM RAM Instantiation
// Copyright (c) 1997 Altera Corporation
// download from: www.pld.com.cn & www.fpga.com.cn
module ram256x8 ( data, address, we, inclock,
www.eeworm.com/read/489686/6468786
v counter.v
// download from: www.pld.com.cn & www.fpga.com.cn
module counter (count, clk, reset);
output [7:0] count;
input clk, reset;
reg [7:0] count;
parameter tpd_clk_to_count = 1;
parameter tp
www.eeworm.com/read/487908/6501804
txt 多路选择器（使用when－else语句）.txt
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
-- download from www.pld.com.cn & www.fpga.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d:
www.eeworm.com/read/487908/6501828
txt 计数器：generic语句的应用.txt
-- n-Bit Synchronous Counter
-- dowload from: www.fpga.com.cn & www.pld.com.cn
LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;
ENTITY cntrnbit IS
GENERIC(
www.eeworm.com/read/487908/6501839
txt 三态总线（注2）.txt
VHDL:Tri-State Buses
download from: http://www.fpga.com.cn
prebus.vhd
LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY prebus IS
PORT(
my_in : IN STD_LOGIC_VECTOR(7 D