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找到约 10,000 项符合「fpga」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/390924/8433395

txt 多路選擇器(使用when－else語句).txt

-- Multiplexer 16-to-4 using if-then-elsif-else Statement -- download from www.pld.com.cn & www.fpga.com.cn library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d:
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www.eeworm.com/read/390924/8433403

txt 三態總線(注2).txt

VHDL:Tri-State Buses download from: http://www.fpga.com.cn prebus.vhd LIBRARY IEEE; USE ieee.std_logic_1164.ALL; ENTITY prebus IS PORT( my_in : IN STD_LOGIC_VECTOR(7 D
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www.eeworm.com/read/433021/8551886

vhd 三态总线.vhd

VHDL:Tri-State Buses download from: http://www.fpga.com.cn prebus.vhd LIBRARY IEEE; USE ieee.std_logic_1164.ALL; ENTITY prebus IS PORT( my_in : IN STD_LOGIC_VECTOR(7 D
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www.eeworm.com/read/167697/9955502

txt 计数器：generic语句的应用.txt

-- n-Bit Synchronous Counter -- dowload from: www.fpga.com.cn & www.pld.com.cn LIBRARY ieee; USE ieee.Std_logic_1164.ALL; USE ieee.Std_logic_unsigned.ALL; ENTITY cntrnbit IS GENERIC(
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www.eeworm.com/read/166954/9988207

txt 多路选择器（使用if－else语句）.txt

-- Multiplexer 16-to-4 using if-then-elsif-else Statement -- download from www.pld.com.cn & www.fpga.com.cn library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d:
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www.eeworm.com/read/166954/9988231

txt 三态总线.txt

VHDL:Tri-State Buses download from: http://www.fpga.com.cn prebus.vhd LIBRARY IEEE; USE ieee.std_logic_1164.ALL; ENTITY prebus IS PORT( my_in : IN STD_LOGIC_VECTOR(7 D
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www.eeworm.com/read/361963/10026211

c dev_c7200_mpfpga.c

/* * Cisco router simulation platform. * Copyright (c) 2005-2007 Christophe Fillot (cf@utc.fr) * * Cisco c7200 Midplane FPGA. */ #include #include #include #inc
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www.eeworm.com/read/361963/10026587

c dev_c6msfc1_mpfpga.c

/* * Cisco router simulation platform. * Copyright (c) 2007 Christophe Fillot (cf@utc.fr) * * MSFC1 Midplane FPGA. */ #include #include #include #include "cpu.h
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www.eeworm.com/read/164962/10080331

txt multiplexer_ifelse.txt

--Multiplexer 16-to-4 using if-then-elsif-else Statement -- download from www.pld.com.cn & www.fpga.com.cn library ieee; use ieee.std_logic_1164.all; entity mux is port( a, b, c, d:
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www.eeworm.com/read/164962/10080391

vhd conversion_altera.vhd

-- MAX+plus II VHDL Example -- Conversion Function -- Copyright (c) 1994 Altera Corporation -- download from: www.pld.com.cn & www.fpga.com.cn LIBRARY ieee; USE ieee.std_logic_1164.all; USE i
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