代码搜索:fen

找到约 1,057 项符合「fen」的源代码

代码结果 1,057
www.eeworm.com/read/127506/14351226

tdo fen_fen_test_v_tf.tdo

## NOTE: Do not edit this file. ## Auto generated by Project Navigator for Verilog Post-PAR Simulation ## vlib work ## Compile Post-PAR Model for Module fen vlog "E:/Xilinx/verilog/src/glbl.v"
www.eeworm.com/read/127506/14351271

fdo fen_fen_test_v_tf.fdo

## NOTE: Do not edit this file. ## Autogenerated by ProjNav (creatfdo.tcl) on Sat Mar 05 11:00:41 中国标准时间 2005 ## vlib work vlog fen.v vlog fen_test.v vlog E:/Xilinx/verilog/src/glbl.v vsim
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mdo fen_fen_test_v_tf.mdo

## NOTE: Do not edit this file. ## Auto generated by Project Navigator for Verilog Post-Map Simulation ## vlib work ## Compile Post-Map Model for Module fen vlog "E:/Xilinx/verilog/src/glbl.v"
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ndo fen_fen_test_v_tf.ndo

## NOTE: Do not edit this file. ## Auto generated by Project Navigator for Verilog Post-Translate Simulation ## vlib work ## Compile Post-Translate Model for Module fen vlog "E:/Xilinx/verilog/s
www.eeworm.com/read/127506/14351434

udo fen_fen_test_v_tf.udo

-- ProjNav VHDL simulation template: fen_fen_test_v_tf.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-defined simulation comm
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sof fen.sof

www.eeworm.com/read/290889/8455605

vhd fen.vhd

library ieee; use ieee.std_logic_1164.all; entity fen is port(clk :in std_logic; q512,q1 :out std_logic); end fen; architecture fen_arc of fen is begin process(clk) v
www.eeworm.com/read/290889/8455609

scf fen.scf

www.eeworm.com/read/388272/8620350

cpp fen.cpp

// fen.cpp // includes #include #include #include "fen.h" // "constants" const char *const start_fen = "rnbqkbnr/pppppppp/8/8/8/8/PPPPPPPP/RNBQKBNR w KQkq - 0 1"; /
www.eeworm.com/read/388272/8620564

h fen.h

// fen.h #ifndef FEN_H #define FEN_H // includes #include "board.h" // "constants" extern const char * const start_fen; // functions extern void board_from_fen(board_t *board,