fen.vhd

来自「这是一个数字中的课程设计」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
entity fen is
port(clk          :in  std_logic;
      q512,q1          :out std_logic);
end fen;
architecture fen_arc of fen is
begin
process(clk)
variable cnt:integer range 0 to 1023;
begin
    if clk'event and clk='1' then
        if cnt<1023 then
            cnt:=cnt+1;
            q1<='0';
        else 
         cnt:=0;
         q1<='1';
       end if;
   end if;
end process;
process(clk)
variable cnt:integer range 0 to 1;
begin
if clk'event and clk='1' then
if cnt<1 then
cnt:=cnt+1;
q512<='0';
else 
cnt:=0;
q512<='1';
end if;
end if;
end process;

end fen_arc;