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Classic Timing Analyzer report for div Wed Apr 16 09:25:01 2008 Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version --------------------- ; Table of Contents ; ---------------------

Assembler report for div Wed Apr 16 09:24:59 2008 Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Noti

Analysis & Synthesis Status : Successful - Wed Apr 16 09:24:51 2008 Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version Revision Name : div Top-level Entity Name : div Family : MAX II To

module div(clk,rst,clk_2,clk_4,clk_8); input clk,rst; output clk_2,clk_4,clk_8; reg [2:0]cnt8; wire clk_2,clk_4,clk_8; always @ (posedge clk or negedge rst) if (!rst) begin cnt8

-- MAX+plus II VHDL Template -- Clearable loadable enablable counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY div IS port (clk_input : in

Project Information d:\laserinterface\cpld\div.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 05/06/2006 15:00:45 Copyright (C) 1988-2002 Al

Fitter report for div Sun Jan 11 21:13:02 2009 Version 6.0 Build 178 04/27/2006 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Fitt

Fitter Status : Successful - Sun Jan 11 21:13:02 2009 Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version Revision Name : div Top-level Entity Name : div Family : MAX II Device : EPM240

/* Quartus II Version 6.0 Build 178 04/27/2006 SJ Full Version */ JedecChain; FileRevision(JESD32A); DefaultMfr(6E); P ActionCode(Cfg) Device PartName(EPM240T100) Path("") File("div.pof")

Analysis & Synthesis report for div Sun Jan 11 21:12:54 2009 Version 6.0 Build 178 04/27/2006 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Not