div.v

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module div(clk,rst,clk_2,clk_4,clk_8);

input clk,rst;
output clk_2,clk_4,clk_8;
reg [2:0]cnt8;

wire clk_2,clk_4,clk_8;

always @ (posedge clk or negedge rst)
	if (!rst)
	begin cnt8<=0;end
	else begin cnt8<=cnt8+1;end

assign clk_2=cnt8[0];
assign clk_4=cnt8[1];
assign clk_8=cnt8[2];

endmodule