代码搜索：ddr_sdram
找到约 113 项符合「ddr_sdram」的源代码
代码结果 113
www.eeworm.com/read/15078/430988
pdf 用xilinx_fpga实现ddr_sdram控制器.pdf
www.eeworm.com/read/375322/9364152
tcl ddr_sdram_rm.tcl
if {[cmp get_assignment_value "" "" "" ROOT] != ""} {
cmp remove_assignment "" "" "" ROOT ""
}
if {[cmp get_assignment_value "" "" "" FAMILY] != ""} {
cmp remove_assignment "" "" "" FAMILY ""
www.eeworm.com/read/224721/14570855
tcl ddr_sdram_rm.tcl
if {[cmp get_assignment_value "" "" "" ROOT] != ""} {
cmp remove_assignment "" "" "" ROOT ""
}
if {[cmp get_assignment_value "" "" "" FAMILY] != ""} {
cmp remove_assignment "" "" "" FAMILY ""
www.eeworm.com/read/393840/8260585
tcl ddr_sdram_rm.tcl
if {[cmp get_assignment_value "" "" "" ROOT] != ""} {
cmp remove_assignment "" "" "" ROOT ""
}
if {[cmp get_assignment_value "" "" "" FAMILY] != ""} {
cmp remove_assignment "" "" "" FAMILY ""
www.eeworm.com/read/103567/15728948
tcl ddr_sdram_rm.tcl
if {[cmp get_assignment_value "" "" "" ROOT] != ""} {
cmp remove_assignment "" "" "" ROOT ""
}
if {[cmp get_assignment_value "" "" "" FAMILY] != ""} {
cmp remove_assignment "" "" "" FAMILY ""
www.eeworm.com/read/375322/9364103
prj ddr_sdram.prj
#-- Synplicity, Inc.
#-- Version 6.0
#-- Project file D:\projects\altera\lpcores\ddr\release\VHDL\V1_0\synthesis\synplicity\ddr_sdram.prj
#-- Written on Fri Jun 30 17:01:13 2000
#add_file opti
www.eeworm.com/read/224721/14570818
prj ddr_sdram.prj
#-- Synplicity, Inc.
#-- Version 6.0
#-- Project file D:\projects\altera\lpcores\ddr\release\VHDL\V1_0\synthesis\synplicity\ddr_sdram.prj
#-- Written on Fri Jun 30 17:01:13 2000
#add_file opti
www.eeworm.com/read/393840/8260497
prj ddr_sdram.prj
#-- Synplicity, Inc.
#-- Version 6.0
#-- Project file D:\projects\altera\lpcores\ddr\release\VHDL\V1_0\synthesis\synplicity\ddr_sdram.prj
#-- Written on Fri Jun 30 17:01:13 2000
#add_file opti
www.eeworm.com/read/103567/15728940
prj ddr_sdram.prj
#-- Synplicity, Inc.
#-- Version 6.0
#-- Project file D:\projects\altera\lpcores\ddr\release\VHDL\V1_0\synthesis\synplicity\ddr_sdram.prj
#-- Written on Fri Jun 30 17:01:13 2000
#add_file opti
www.eeworm.com/read/359197/10161714
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ddr_sdram is
port(
clk : in vl_logic;
reset_n : in vl_logic;
addr : in vl_logic