代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/339148/12255251
txt readme.txt
I/O inputs -
Inputs :
datain (8 bits) = serial input where message data is fed. If the message polynomial of form,
d_nX^n + d_(n-1)X^(n-1) + ......etc., then d_n followed by d_(n-1) in the
www.eeworm.com/read/118409/14873186
java ch6_e6_30.java
public class ch6_e6_30
{
public static void main(String args[])
{
int[] dataIn = {49,45,80,11,18,106,55,251,91};//欲放入二叉树中的数据
BinaryTree searchTree = new BinaryTree(dataI
www.eeworm.com/read/115479/15013090
txt readme.txt
I/O inputs -
Inputs :
datain (8 bits) = serial input where message data is fed. If the message polynomial of form,
d_nX^n + d_(n-1)X^(n-1) + ......etc., then d_n followed by d_(n-1) in the
www.eeworm.com/read/211745/15174590
vhd d_flipflop.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity D_flipflop is
port(ri,clk:in std_logic;
datain :in std_logic_vector(7 downto 0);
www.eeworm.com/read/14792/410823
vhd d_flipflop.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity D_flipflop is
port(ri,clk:in std_logic;
datain :in std_logic_vector(7 downto 0);
www.eeworm.com/read/17609/742692
vhd d_flipflop.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity D_flipflop is
port(ri,clk:in std_logic;
datain :in std_logic_vector(7 downto 0);
www.eeworm.com/read/17895/766275
vhd d_flipflop.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity D_flipflop is
port(ri,clk:in std_logic;
datain :in std_logic_vector(7 downto 0);
www.eeworm.com/read/17921/767252
vhd d_flipflop.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity D_flipflop is
port(ri,clk:in std_logic;
datain :in std_logic_vector(7 downto 0);
www.eeworm.com/read/18031/771507
vhd d_flipflop.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity D_flipflop is
port(ri,clk:in std_logic;
datain :in std_logic_vector(7 downto 0);
www.eeworm.com/read/18253/782456
vhd d_flipflop.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity D_flipflop is
port(ri,clk:in std_logic;
datain :in std_logic_vector(7 downto 0);