d_flipflop.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity D_flipflop is
port(ri,clk:in std_logic;
	datain :in std_logic_vector(7 downto 0);
	dataout :out std_logic_vector(7 downto 0);
	wr:out std_logic);
end D_flipflop;
architecture behav of D_flipflop is
signal sig1,sig2:std_logic;
signal count:std_logic_vector(1 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1')then
	if(ri='0')then
		dataout<=datain;
		
		if(sig1='0' and sig2='1' )then
			if(count="10" )then
				count<="00";
				wr<='0';
				sig1<='1';
			else
				count<=count+'1';
				wr<='1';
			end if;
		end if;
	else
		sig1<='0';
		sig2<='1';
	end if;

		
end if;

end process;
end behav;