代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/18031/771606
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk
www.eeworm.com/read/18253/782556
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk
www.eeworm.com/read/18342/784974
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk
www.eeworm.com/read/18488/791275
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk
www.eeworm.com/read/303435/3813101
kz jpfile.kz
Migration parameters
================
datain=stdin
dataout=stdout
ttfile=ttime
nzt=60 fzt=0 dzt=50
nxt=100 fxt=0 dxt=100
ns=30 fs=1000 ds=100
nzo=150 fzo=0 dzo=10
nxo=2 fxo=2000 dxo=
www.eeworm.com/read/302096/3827033
tgt coord.tgt
/* $XORP: xorp/xrl/targets/coord.tgt,v 1.1.1.1 2002/12/11 23:56:18 hodson Exp $ */
#include "common.xif"
#include "coord.xif"
#include "datain.xif"
target coord implements common/0.1, coord/0.1, dat
www.eeworm.com/read/296366/3904422
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk
www.eeworm.com/read/263726/4299766
tgt coord.tgt
/* $XORP: xorp/xrl/targets/coord.tgt,v 1.2 2004/04/10 07:41:42 pavlin Exp $ */
#include "common.xif"
#include "coord.xif"
#include "datain.xif"
target coord implements common/0.1, \
coord/0.
www.eeworm.com/read/369333/9654518
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk
www.eeworm.com/read/248277/12586515
vhd fifo.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is
port( DataIn :in std_logic_vector(7 downto 0);
DataOut :out std_logic_vector(7 downto 0);
clk