fifo.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo is 
	port(	DataIn	:in std_logic_vector(7 downto 0);
			DataOut	:out std_logic_vector(7 downto 0);
			clk		:in std_logic;					--rising is valid
			clr		:in std_logic;					--clear '0' is valid
			wr		:in std_logic;					--write '0' is valid
			rd		:in std_logic;					--read '0' is valid
			empty	:out std_logic;				--stack is empty ,'1' is valid
			full		:out std_logic				--stack is full, '1' is valid
		);
end fifo;
architecture beh of fifo is 
	COMPONENT altdpram
	GENERIC (
		WIDTH		: NATURAL;
		WIDTHAD		: NATURAL;
		INDATA_REG		: STRING;
		WRADDRESS_REG		: STRING;
		WRCONTROL_REG		: STRING;
		RDADDRESS_REG		: STRING;
		RDCONTROL_REG		: STRING;
		OUTDATA_REG		: STRING;
		INDATA_ACLR		: STRING;
		WRADDRESS_ACLR		: STRING;
		WRCONTROL_ACLR		: STRING;
		RDADDRESS_ACLR		: STRING;
		RDCONTROL_ACLR		: STRING;
		OUTDATA_ACLR		: STRING;
		LPM_HINT		: STRING
	);
	PORT (
			wren	: IN STD_LOGIC ;
			inclock	: IN STD_LOGIC ;
			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			rdaddress	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
			wraddress	: IN STD_LOGIC_VECTOR (8 DOWNTO 0)
	);
	END COMPONENT;
	signal pw:std_logic_vector(9-1 downto 0);		--point to next writting unit.
	signal pr:std_logic_vector(9-1 downto 0);		--point to current reading unit.
	signal sub_full,sub_empty:std_logic;			--connect to full and empty;
	signal wren:std_logic;						--connect to dp_ram wren;
begin
	altdpram_component : altdpram
	GENERIC MAP (
		WIDTH => 8,
		WIDTHAD => 9,
		INDATA_REG => "INCLOCK",
		WRADDRESS_REG => "INCLOCK",
		WRCONTROL_REG => "INCLOCK",
		RDADDRESS_REG => "UNREGISTERED",
		RDCONTROL_REG => "UNREGISTERED",
		OUTDATA_REG => "UNREGISTERED",
		INDATA_ACLR => "OFF",
		WRADDRESS_ACLR => "OFF",
		WRCONTROL_ACLR => "OFF",
		RDADDRESS_ACLR => "OFF",
		RDCONTROL_ACLR => "OFF",
		OUTDATA_ACLR => "OFF",
		LPM_HINT => "USE_EAB=ON"
	)
	PORT MAP (
		wren => wren,	--when wren is '0' disable write.
		inclock => clk,
		data => DataIn,
		rdaddress => pr,
		wraddress => pw,
		q => DataOut
	);
	wren<=(not sub_full)and(not wr);		--when not full and wr='0' allow write.
	full<=sub_full;
	empty<=sub_empty;
	--------------- process of write and read.---------------
	process(clk,clr)
	begin
		if(clr = '0')then
			pw<="000000000";
			pr<="111111111";
		elsif(clk'event and clk='1')then
			if(sub_full='0' and wr='0')then
				pw<=pw+"000000001";
			end if;
			if(sub_empty ='0' and rd='0')then
				pr<=pr+"000000001";
			end if;
		end if;
	end process;
	--------------- process deal with sub_empty and sub_full---------------
	process(clk,clr)
	variable Nextpr:std_logic_vector(9-1 downto 0);
	begin
		if(clr='0')then
			sub_empty<='0';
		elsif(clk'event and clk='1')then
			if(rd='0' and wr='1')then						--only read ,no write.
				Nextpr:=pr+"000000010";
				if(Nextpr=pw)then
					sub_empty<='1';
				end if;
			elsif(wr='0' and rd='1' and sub_empty='1')then	--cancel empty
				sub_empty<='0';
			end if;
		end if;
	end process;
	process(clk,clr)
	begin
		if(clr='0')then
			sub_full<='0';
		elsif(clk'event and clk='1')then
			if(rd='1' and wr='0')then						--only write, no read.
				if(pr=pw)then
					sub_full<='1';
				end if;
			elsif(wr='1' and rd='0' and sub_full='1')then		--cancel full
				sub_full<='0';
			end if;
		end if;
	end process;
end beh;