代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
www.eeworm.com/read/17918/767009

vhd ad.vhd

--AD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity ad is port(busy:in std_logic; datain:in unsigned(7 downto 0); clk:in std_logic; dataout:out un
www.eeworm.com/read/17921/767285

vhd ad.vhd

--AD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity ad is port(busy:in std_logic; datain:in unsigned(7 downto 0); clk:in std_logic; dataout:out un
www.eeworm.com/read/17921/767362

vhd counter_1024.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter_1024 is port(clk,clr,en,updn,bcdwr:in std_logic; datain:in std_logic_vector(9 downt
www.eeworm.com/read/18022/770851

vhd sin3.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY sin3 IS PORT(clk:IN STD_LOGIC; datain:IN STD_LOGIC; mclk:IN STD_LOGIC; sel:IN STD_LOGIC_VECTOR(1 DOWNTO 0); ad:OU
www.eeworm.com/read/18031/771540

vhd ad.vhd

--AD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity ad is port(busy:in std_logic; datain:in unsigned(7 downto 0); clk:in std_logic; dataout:out un
www.eeworm.com/read/18031/771617

vhd counter_1024.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter_1024 is port(clk,clr,en,updn,bcdwr:in std_logic; datain:in std_logic_vector(9 downt
www.eeworm.com/read/18253/782490

vhd ad.vhd

--AD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity ad is port(busy:in std_logic; datain:in unsigned(7 downto 0); clk:in std_logic; dataout:out un
www.eeworm.com/read/18253/782567

vhd counter_1024.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter_1024 is port(clk,clr,en,updn,bcdwr:in std_logic; datain:in std_logic_vector(9 downt
www.eeworm.com/read/18342/784908

vhd ad.vhd

--AD library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity ad is port(busy:in std_logic; datain:in unsigned(7 downto 0); clk:in std_logic; dataout:out un
www.eeworm.com/read/18342/784985

vhd counter_1024.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter_1024 is port(clk,clr,en,updn,bcdwr:in std_logic; datain:in std_logic_vector(9 downt