counter_1024.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter_1024 is
       port(clk,clr,en,updn,bcdwr:in std_logic;
            datain:in std_logic_vector(9 downto 0);
			c:out std_logic;
            q:out std_logic_vector (9 downto 0));
end counter_1024;

architecture rtl of counter_1024 is
signal count_10:std_logic_vector(9 downto 0);
--signal temp_14:std_logic_vector(13 downto 0);
begin
    q(0)<=count_10(0);
    q(1)<=count_10(1);
    q(2)<=count_10(2);
    q(3)<=count_10(3);
	q(4)<=count_10(4);
	q(5)<=count_10(5);
	q(6)<=count_10(6);
	q(7)<=count_10(7);
	q(8)<=count_10(8);
	q(9)<=count_10(9);
	c<=count_10(0) and count_10(1) and count_10(2) and count_10(3) and count_10(4) and count_10(5) and count_10(6) and count_10(7) and count_10(8) and count_10(9);
   process(clk,clr,bcdwr)
       begin
		if clk'event and clk='1'   then
		if en='0' then
		count_10<=count_10;
		elsif clr='1'then
		count_10<="0000000000";
		elsif bcdwr='1' then
		count_10<=datain;
		elsif updn='1' then
		count_10<=count_10+'1';
		else count_10<=count_10-'1';
		end if;
		end if;
	end process;
end rtl;