代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/159015/10701696
txt readme.txt
1. compile:
mpicc invert.c -o invert
2. run:
mpirun -np 4 invert
3. result( in file dataOut.txt):
Input of file "dataIn.txt"
3 3
1.000000 -1.000000 1.000000
5.000000
www.eeworm.com/read/264253/11324054
txt readme.txt
1. compile:
mpicc invert.c -o invert
2. run:
mpirun -np 4 invert
3. result( in file dataOut.txt):
Input of file "dataIn.txt"
3 3
1.000000 -1.000000 1.000000
5.000000
www.eeworm.com/read/17582/739976
vhd segmain.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity segmain is
PORT( clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
datain : IN STD_LOGIC_VECTOR(15 DO
www.eeworm.com/read/303435/3811104
main trip.mesa.main
TRIP - TRI-Plane 3D data viewer
trip < datain [parameters]
Required parameters:
n1= number of x samples (1st dimension)
n2= number of y samples (2nd dimensio
www.eeworm.com/read/390455/8464815
vhd dcnt6.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DCNT6 IS
PORT(CLK:IN STD_LOGIC;
LOAD:IN STD_LOGIC;
ENA: IN STD_LOGIC;
DATAIN:IN STD
www.eeworm.com/read/289462/8549324
vhd recehdlc.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ReceHDLC is
port (
reset,clk : in std_logic;
DataIn : in std_logic;
www.eeworm.com/read/188087/8573563
txt readme.txt
1. compile:
mpicc jacobi.c -o jacobi
2. run:
mpirun -np 4 jacobi
3. result (also in file dataOut.txt):
Input of file "dataIn.txt"
4 5
9.000000 -1.000000 -1.000000 1
www.eeworm.com/read/181930/9225119
txt readme.txt
1. compile:
mpicc jacobi.c -o jacobi
2. run:
mpirun -np 4 jacobi
3. result (also in file dataOut.txt):
Input of file "dataIn.txt"
4 5
9.000000 -1.000000 -1.000000 1
www.eeworm.com/read/364784/9895728
vhd recehdlc.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ReceHDLC is
port (
reset,clk : in std_logic;
DataIn : in std_logic;
www.eeworm.com/read/301737/10048102
vhd send.vhd
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
entity send is
port
(
clk16x : in std_logic;
clk : in std_logic;
ctrl : in std_logic;
datain : in