代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/381853/2640073
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_routing_wire is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end cyclone_routing_wire
www.eeworm.com/read/381853/2640206
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity oper_latch is
port(
datain : in vl_logic;
dataout : out vl_logic;
latch_enable : in vl_logi
www.eeworm.com/read/381853/2640215
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity io_buf_opdrn is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end io_buf_opdrn;
www.eeworm.com/read/353157/3089668
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_routing_wire is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end cyclone_routing_wire
www.eeworm.com/read/260612/4329997
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity io_buf_opdrn is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end io_buf_opdrn;
www.eeworm.com/read/260612/4330182
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity io_buf_opdrn is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end io_buf_opdrn;
www.eeworm.com/read/472904/6859620
vhd sramcontroller.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---------------------------------------
entity sramcontroller is
port
(clock:in std_logic;
datain:in std_logic_vecto
www.eeworm.com/read/336008/12482966
java netc.java
import java.net.*;
import java.io.*;
import java.awt.*;
import java.lang.*;
public class Netc
{
static Socket sock[];
static InetAddress Serveraddr[];
static DataInputStream datain[
www.eeworm.com/read/488558/6489623
h readdata.h
//////读入数据类
#ifndef _READDATA_H_
#define _READDATA_H_
#include
class CReadData
{
public:
CReadData();
virtual~CReadData();
ifstream datain;
/////计算控制变量
int BusOpti
www.eeworm.com/read/16514/676639
esf lp_rx_top_stratix.esf
OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
{
datain : FAST_INPUT_REGISTER = OFF;
inclock : STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS = OFF;
rdata : VIRTUAL_PIN = ON;
empty : VIRTUAL_PIN = ON;
r