lp_rx_top_stratix.esf

来自「altera fpga 和ts201的linkport接口设计」· ESF 代码 · 共 18 行

OPTIONS_FOR_INDIVIDUAL_NODES_ONLY
{
	datain : FAST_INPUT_REGISTER = OFF;
	inclock : STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS = OFF;
	rdata : VIRTUAL_PIN = ON;
	empty : VIRTUAL_PIN = ON;
	rcser : VIRTUAL_PIN = ON;
	rdreq : VIRTUAL_PIN = ON;
	rvere : VIRTUAL_PIN = ON;
}
TIMING_REQUIREMENTS
{
	inclock : CLOCK_SETTINGS = inclock;
	datain : TH_REQUIREMENT = .45ns;
	datain : TSU_REQUIREMENT = .45ns;
	rvere -> * : CUT = ON;
}