代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/338256/3319029
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ddr_clk is
port(
datain_h : in vl_logic;
clk : in vl_logic;
dataout : out vl_logic
www.eeworm.com/read/338256/3319075
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity oper_latch is
port(
datain : in vl_logic;
dataout : out vl_logic;
latch_enable : in vl_logi
www.eeworm.com/read/338256/3319084
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixii_lvds_rx_fifo_sync_ram is
port(
clk : in vl_logic;
datain : in vl_logic;
write_reset
www.eeworm.com/read/338256/3319110
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity lp_rx is
port(
clk : in vl_logic;
rst_n : in vl_logic;
datain : in vl_logic_vec
www.eeworm.com/read/338256/3319170
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity io_buf_opdrn is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end io_buf_opdrn;
www.eeworm.com/read/338256/3319339
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity oper_latch is
port(
datain : in vl_logic;
dataout : out vl_logic;
latch_enable : in vl_logi
www.eeworm.com/read/338256/3319348
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity io_buf_opdrn is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end io_buf_opdrn;
www.eeworm.com/read/316255/3612429
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_routing_wire is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end cyclone_routing_wire
www.eeworm.com/read/270378/4239607
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cyclone_routing_wire is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end cyclone_routing_wire
www.eeworm.com/read/268991/4247980
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity maxii_routing_wire is
port(
datain : in vl_logic;
dataout : out vl_logic
);
end maxii_routing_wire;