代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
www.eeworm.com/read/397063/2404613

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity register5_wl is generic( width : integer := 8 ); port( datain : in vl_logic_vector; dataout
www.eeworm.com/read/402457/6786100

v rsc_7_5encoder.v

/* ------------------------------------------------------------------------- Author:QiuPing Zhong Date:Oct 18th,2004 Veision: Function:complete RSC_7_5encoder CLK: DataIn_Speed: DataOut_Spee
www.eeworm.com/read/402457/6786109

v interrsc_7_5encoder.v

/* ------------------------------------------------------------------------- Author:QiuPing Zhong Date:Oct 18th,2004 Veision: Function:complete RSC_7_5encoder CLK: DataIn_Speed: DataOut_Spee
www.eeworm.com/read/366926/9792590

java calcworker.java

import java.io.*; import java.net.*; public class CalcWorker extends Object { private InputStream sockIn; private OutputStream sockOut; private DataInputStream dataIn; private DataOutputSt
www.eeworm.com/read/103425/15733163

java calcworker.java

import java.io.*; import java.net.*; public class CalcWorker extends Object { private InputStream sockIn; private OutputStream sockOut; private DataInputStream dataIn; private DataOutputSt
www.eeworm.com/read/427429/8945544

v sdram_controller.v

module Sdram_Controller( // HOST REF_CLK, RESET_N, ADDR, WR, RD, LENGTH, ACT, DONE, DATAIN, DATAOUT, IN_REQ, OUT_VALID, DM
www.eeworm.com/read/321790/13398748

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity hssi_tx is generic( channel_width : integer := 1 ); port( clk : in vl_logic; datain : i
www.eeworm.com/read/347114/11690853

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity hssi_tx is generic( channel_width : integer := 1 ); port( clk : in vl_logic; datain : i
www.eeworm.com/read/347114/11691583

vhd _primary.vhd

library verilog; use verilog.vl_types.all; entity apexii_pterm_register is generic( power_up : string := "low" ); port( datain : in vl_logic; c
www.eeworm.com/read/345531/11810010

v sdram_controller.v

module Sdram_Controller( // HOST REF_CLK, RESET_N, ADDR, WR, RD, LENGTH, ACT, DONE, DATAIN, DATAOUT, IN_REQ, OUT_VALID, DM