interrsc_7_5encoder.v

turbo码_verilog_编码源文件

/*	-------------------------------------------------------------------------
Author:QiuPing Zhong
Date:Oct 18th,2004
Veision: 

Function:complete RSC_7_5encoder
CLK:
DataIn_Speed:
DataOut_Speed:
---------------------------------------------------------------------------*/
module interRSC_7_5encoder(//input:
                     data_clk,
                     reset_n,
							framehead,
							bitin,
							tailinen,
							//output:
							sysbitout,
							paribitout
                     );
  
  input data_clk;
  input reset_n;
  input framehead;
  input bitin;
  input tailinen;
  
  output sysbitout;
  output paribitout;
 
  
  parameter IDLE=2'd0, A=2'd1, B=2'd2,C=2'd3; //the four state of RSC_7_5 encoder

  reg [1:0] current_state;
  reg [1:0] next_state;
  reg [2:0] cnt4;
  //wire tailen;
  
  reg sysbitout;
  reg paribitout;
 
always@(posedge data_clk or posedge reset_n)
begin 
  if(reset_n)
    cnt4<=3'd4;
  else if(tailinen)
       cnt4<=0;
		 else if(!cnt4[2])
		      cnt4<=cnt4+1;
end

//assign tailen=!cnt4[2];

/*  state swicthing with all the possible conditions,see details in word file */
always@(posedge data_clk or posedge reset_n)
begin
    if(reset_n)
	   current_state<=IDLE;
    else if(framehead)
	       current_state<=IDLE; 
	      else current_state<=next_state;
end

always@(current_state or cnt4[2] or bitin)
begin
if(cnt4[2])   
     case(current_state)
       IDLE: if(bitin)
		         next_state<=B;
             else 
					next_state<=IDLE;
        A:	 if(bitin)
		         next_state<=IDLE;
             else 
					next_state<=B;
        B:   if(bitin)
		         next_state<=A;
             else 
					next_state<=C;
        C:   if(bitin)
		         next_state<=C;
             else 
					next_state<=A;        
    endcase
else
    case(current_state)
       IDLE: next_state<=IDLE;
        A:	 next_state<=IDLE;
        B:   next_state<=IDLE;
        C:   next_state<=A;
    endcase
end


always@(posedge data_clk or posedge reset_n)
begin
    if(reset_n)
	   begin
	    sysbitout<=0;
	    paribitout<=0;
	   end
	 else if(cnt4[2])
	         begin
	         case(current_state)
				IDLE: if(bitin)
				          begin
				           sysbitout<=1;
	                    paribitout<=1;
						    end
				      else 
						    begin
				           sysbitout<=0;
	                    paribitout<=0;
						    end
            A:	   if(bitin)
				          begin
				           sysbitout<=1;
	                    paribitout<=1;
						    end
				      else 
						    begin
				           sysbitout<=0;
	                    paribitout<=0;
						    end
            B:	   if(bitin)
				          begin
				           sysbitout<=1;
	                    paribitout<=0;
						    end
				      else 
						    begin
				           sysbitout<=0;
	                    paribitout<=1;
						    end
            C:	   if(bitin)
				          begin
				           sysbitout<=1;
	                    paribitout<=0;
						    end
				      else 
						    begin
				           sysbitout<=0;
	                    paribitout<=1;
						    end
				endcase
	         end
        else
		      begin
	         case(current_state)
				IDLE: begin
				      sysbitout<=0;
	               paribitout<=0;
						end
            A:	   begin
				      sysbitout<=1;
	               paribitout<=1;
						end
            B:	   begin
				      sysbitout<=1;
	               paribitout<=0;
						end
            C:	   begin
				      sysbitout<=0;
	               paribitout<=1;
						end
				endcase
				end
end		      



endmodule