代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/421254/10746511
c logic.c
#include
#include
//#include
//#include
#include "logic.h"
#define DATAIN PINA
#define DATADIR DDRA
#define DATAOUT PORTA
#defi
www.eeworm.com/read/350244/10755241
rpt code.tan.rpt
Classic Timing Analyzer report for code
Wed Jun 25 21:11:15 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
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www.eeworm.com/read/349548/10819790
vhd sn7448.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sn7448 is
port(lt,rbi:std_logic;
datain:in std_logic_vector(3 downto 0);
rbo_b
www.eeworm.com/read/468159/6994534
usbbus_hier_info
|usbbus
PD2 PD2.DATAIN
WRN WRN.DATAIN
WR => 74244b:inst.AGN
WR => 74244b:inst.BGN
RDN
www.eeworm.com/read/398287/7105208
hier_info ep2c5q208.hier_info
|EP2C5Q208
TXD UART:inst7.RESET
RESET => Frequency:inst.RESET
RESET => irDA:inst6.RESET
RESET => LCD1602:inst2.RESET
RESET => Operation:inst13.RESET
RESET => KeyBoard
www.eeworm.com/read/463172/7186638
v dtsmg.v
module dtsmg(main_clk,rst,datain,bcd_led,ledcom,com_clk);
input main_clk,rst;
input [15:0] datain;
output [1:0] com_clk;
output [3:0] ledcom;
output [3:0] bcd_led;
reg [3:0] ledcom,bcd_
www.eeworm.com/read/463166/7186709
v dtsmg.v
module dtsmg(main_clk,rst,datain,bcd_led,ledcom,com_clk);
input main_clk,rst;
input [7:0] datain;
output [1:0] com_clk;
output [3:0] ledcom;
output [3:0] bcd_led;
reg [3:0] ledcom,bcd_l
www.eeworm.com/read/460213/7255634
vhd sn7448.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sn7448 is
port(lt,rbi:std_logic;
datain:in std_logic_vector(3 downto 0);
rbo_b
www.eeworm.com/read/448916/7522343
fit reg32.fit
-- MAX+plus II Compiler Fit File
-- Version 10.0 9/14/2000
-- Compiled: 11/15/2004 16:08:08
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and