代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
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bak segmain.v.bak

module segmain(clk,reset_n,datain,seg_data,seg_com); input clk; input reset_n; input [15:0] datain; output [7:0]seg_data; output [3:0]seg_com; reg [3:0]seg_com; reg [7:0]seg_data; reg [3:0
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v segmain.v

module segmain(clk,reset_n,datain,seg_data,seg_com); input clk; input reset_n; input [15:0] datain; output [7:0]seg_data; output [3:0]seg_com; reg [3:0]seg_com; reg [7:0]seg_data; reg [3:0
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h header.h

#ifndef W90P71_EBI_H_ #define W90P71_EBI_H_ #endif /*W90P71_EBI_H_*/ #define GETBIT(REG,N) (REG&(1
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vhdl hammingenc4sets512byte.vhdl

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for ins
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v transmit.v

module transmit( clk125, rst, souadd, mode, /******/ desadd, headadd,
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vhd sn7448.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sn7448 is port(lt,rbi:std_logic; datain:in std_logic_vector(3 downto 0); rbo_b
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hier_info tri_s11_1.hier_info

|tri_s11_1 enaddr => oaddrDSP[10]~10.OE enaddr => oaddrDSP[9]~9.OE enaddr => oaddrDSP[8]~8.OE enaddr => oaddrDSP[7]~7.OE enaddr => oaddrDSP[6]~6.OE enaddr => oaddrDSP[5]~5.OE enaddr => oaddrDSP
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hier_info tri_s8_1.hier_info

|tri_s8_1 endata3 => odataDSP[7]~7.OE endata3 => odataDSP[6]~6.OE endata3 => odataDSP[5]~5.OE endata3 => odataDSP[4]~4.OE endata3 => odataDSP[3]~3.OE endata3 => odataDSP[2]~2.OE endata3 => odat
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vhd sn7448.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sn7448 is port(lt,rbi:std_logic; datain:in std_logic_vector(3 downto 0); rbo_b
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hier_info ep2c5q208.hier_info

|EP2C5Q208 TXD UART:inst7.RESET RESET => Frequency:inst.RESET RESET => irDA:inst6.RESET RESET => LCD1602:inst2.RESET RESET => Operation:inst13.RESET RESET => KeyBoard