代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/419416/10869918
vhd data_part.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
www.eeworm.com/read/417885/10972075
hier_info disturb.hier_info
|Disturb
disturb Dif:D0.clk
CLK => Dif:D1.clk
CLK => Dif:D2.clk
CLK => Dif:D3.clk
CLK => Dif:D4.clk
CLK => Dif:D5.clk
CLK => Dif:D6.clk
CLK => Dif:D7.cl
www.eeworm.com/read/416057/11043046
vhd dataoutmux.vhd
--****************************************************************************************************
-- Data out register for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 04.12.2002
--**
www.eeworm.com/read/416057/11043108
vhd resltbitmask.vhd
--****************************************************************************************************
-- This module cleares/sets bit 0 and clears 1 of ALU bus for ARM7TDMI-S processor
-- Designed
www.eeworm.com/read/470943/6902167
hier_info piso.hier_info
|PiSo
clk => q[0].CLK
clk => q[1].CLK
clk => q[2].CLK
clk => q[3].CLK
clk => q[4].CLK
clk => q[5].CLK
clk => q[6].CLK
clk => q[7].CLK
clk => cnt[0].CLK
clk => cnt[1].CLK
clk => cnt[2].CLK
www.eeworm.com/read/471028/6904257
hier_info top.hier_info
|top
clk => clk~0.IN6
clkout clk2~reg0.CLK
clk2 c.CLK
clk => e.CLK
www.eeworm.com/read/460213/7255326
vhd testda.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity testda is
port(clk:in std_logic;
data:out std_logic_vector(7 downto 0);
www.eeworm.com/read/458604/7293328
hier_info original_signal.hier_info
|original_signal
pin_name altpll0:inst6.inclk0
RstN => frecontr:inst2.rstn
RstN => inst7.IN0
RstN => mod:inst4.rstn
RstN => datarom:inst.RstN
dataout[4]
www.eeworm.com/read/448916/7522449
vhd reg32.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port(load:in std_logic;
datain:in std_logic_vector(31 downto 0);
dataout:out std_logic_vector(31 downto 0));
end entity;