代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/224286/14598095
hier_info subdir.hier_info
|SubDir
AU 36.CLK
clk => 35.CLK
clk => 38.CLK
clk => 37.CLK
A => 36.DATAIN
A => inst2.IN0
A => 9.IN0
A => 18.IN0
AD
www.eeworm.com/read/223485/14638914
vhd receive_filter.vhd
-------------------------------------------------------------------------------
-- Title : 接收端48阶波形形成滤波器（升余弦）
-- Project :
-----------------------------------------------------------------
www.eeworm.com/read/214366/15104726
vhd reg.vhd
-- reg.vhd
-- This module implements a 16-bit general purpose register. The contents of
-- register is loaded on the rising edge of "clk". It is cleared to zero when
-- "reset" is asserted low. T
www.eeworm.com/read/213740/15126580
vhd clock24coms.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE clock24coms IS
COMPONENT jsq60
PORT(clk:IN STD_LOGIC;
en0,en1,cin:IN STD_LOGIC;
datain:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
www.eeworm.com/read/209607/15216611
qsf dial1.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
www.eeworm.com/read/209607/15216614
rpt dial1.tan.rpt
Timing Analyzer report for DIAL1
Sat Apr 28 17:41:54 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
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html merge_files.html
/
[Master Index]
[Index for ./main]
merge_files
(./main/merge_files.m)
Function Synopsis
www.eeworm.com/read/153670/5645516
v eth_registers.v
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_registers.v
www.eeworm.com/read/475608/6774289
bak test.v.bak
`timescale 10ns/1ns
module test;
reg clk;
reg reset;
reg ena;
reg [15:0] datain;
wire [15:0] I_out;
wire [15:0] Q_out;
wire [1:0] cout;
initial
begin
clk=0;
reset=1'b0;
ena=1'b1;
datain=16'b0;
#