receive_filter.vhd

VHDL语言实现了IS-95标准中的48阶成型滤波器。工作速率80Mbps。接收发送端均可使用。

-------------------------------------------------------------------------------
-- Title      : 接收端48阶波形形成滤波器（升余弦）
-- Project    : 
-------------------------------------------------------------------------------
-- File       : receive_filter.vhd
-- Author     :   <litianwei>
-- Company    :   ELE PKU
-- Created    : 2004-12-22
-- Last update: 2004-12-27
-- Platform   : 
-- Standard   : 
-------------------------------------------------------------------------------
-- Description: input is expressed in 9 bit and the coefficients of the filter 
-- are expressed in CSD.
-- 
-------------------------------------------------------------------------------
-- Copyright (c) 2004 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author     Description
-- 2004-12-27  1.0      litianwei	Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
--use ieee.std_logic_arith.all;

entity receive_filter is
  port( 
    datain: in std_logic_vector(8 downto 0) :="000000000";
    dout: out std_logic_vector(19 downto 0) :="00000000000000000000";   
    clock: in std_logic
    );
end;

architecture a of receive_filter is

  type rcvdelay is array (47 downto 1) of std_logic_vector(19 downto 0);
  signal D: rcvdelay :=("00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000",
"00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000",
"00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000",
"00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000",
"00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000",
"00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000",
"00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000",
"00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000",
"00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000","00000000000000000000");
 

	signal G1_t1x : std_logic_vector(8 downto 0) :="000000000";
	signal G1_t2x : std_logic_vector(10 downto 0) :="00000000000";
	signal G1_t8x : std_logic_vector(12 downto 0):="0000000000000";
	signal G1_t16x: std_logic_vector(13 downto 0) :="00000000000000";
	

	signal G2_t1x : std_logic_vector(8 downto 0) :="000000000";
	signal G2_t2x : std_logic_vector(10 downto 0):="00000000000";
	signal G2_t8x : std_logic_vector(12 downto 0):="0000000000000";
	signal G2_t16x: std_logic_vector(13 downto 0):="00000000000000";
	signal G2_t3x: std_logic_vector(10 downto 0):="00000000000";
	signal G2_t7x: std_logic_vector(12 downto 0):="0000000000000";
	signal G2_t9x: std_logic_vector(12 downto 0):="0000000000000";
	signal G2_t17x: std_logic_vector(13 downto 0) :="00000000000000";
	

	signal G3_t1x : std_logic_vector(8 downto 0) :="000000000";
	signal G3_t2x : std_logic_vector(10 downto 0) :="00000000000";
	signal G3_t8x : std_logic_vector(12 downto 0):="0000000000000";
	signal G3_t16x: std_logic_vector(13 downto 0) :="00000000000000";
	signal G3_t3x: std_logic_vector(10 downto 0) :="00000000000";
	signal G3_t7x: std_logic_vector(12 downto 0):="0000000000000";
	signal G3_t9x: std_logic_vector(12 downto 0):="0000000000000";
	signal G3_t17x: std_logic_vector(13 downto 0) :="00000000000000";	
	signal G3_t12x: std_logic_vector(13 downto 0) :="00000000000000";
	signal G3_t14x: std_logic_vector(14 downto 0) :="000000000000000";  
	signal G3_t24x: std_logic_vector(14 downto 0) :="000000000000000";	
	signal G3_t28x: std_logic_vector(15 downto 0) :="0000000000000000";
	signal G3_t36x: std_logic_vector(15 downto 0) :="0000000000000000"; 	
	signal G3_t112x: std_logic_vector(17 downto 0) :="000000000000000000";
	signal G3_t192x: std_logic_vector(17 downto 0) :="000000000000000000";	
	


	signal G4_t2x : std_logic_vector(10 downto 0) :="00000000000";
	signal G4_t16x: std_logic_vector(13 downto 0) :="00000000000000";
	signal G4_t3x: std_logic_vector(10 downto 0) :="00000000000";
	signal G4_t9x: std_logic_vector(12 downto 0):="0000000000000";
	signal G4_t17x: std_logic_vector(13 downto 0) :="00000000000000";	
	signal G4_t24x: std_logic_vector(14 downto 0) :="000000000000000";	
	signal G4_t36x: std_logic_vector(15 downto 0) :="0000000000000000"; 	
	signal G4_t112x: std_logic_vector(17 downto 0) :="000000000000000000";
	signal G4_t192x: std_logic_vector(17 downto 0) :="000000000000000000";		
	signal G4_t11x: std_logic_vector(12 downto 0):="0000000000000";
	signal G4_t13x: std_logic_vector(13 downto 0) :="00000000000000";
	signal G4_t21x: std_logic_vector(14 downto 0) :="000000000000000";
	signal G4_t23x: std_logic_vector(14 downto 0) :="000000000000000";
	signal G4_t27x: std_logic_vector(15 downto 0) :="0000000000000000";
	signal G4_t37x: std_logic_vector(15 downto 0) :="0000000000000000";
	signal G4_t113x: std_logic_vector(17 downto 0) :="000000000000000000";
	signal G4_t201x: std_logic_vector(17 downto 0) :="000000000000000000";
	
	
	signal o4x : std_logic_vector(11 downto 0):="000000000000";	
	signal o6x : std_logic_vector(11 downto 0):="000000000000";	
	signal o22x: std_logic_vector(13 downto 0) :="00000000000000";
	signal o54x: std_logic_vector(16 downto 0) :="00000000000000000";
	signal o32x: std_logic_vector(14 downto 0) :="000000000000000";
	signal o256x: std_logic_vector(17 downto 0) :="000000000000000000";		
	
	signal o9x: std_logic_vector(12 downto 0):="0000000000000";
	signal o17x: std_logic_vector(13 downto 0) :="00000000000000";	
	signal o21x: std_logic_vector(14 downto 0) :="000000000000000";
	signal o23x: std_logic_vector(14 downto 0) :="000000000000000";
	signal o16x: std_logic_vector(13 downto 0) :="00000000000000";
	signal o13x: std_logic_vector(13 downto 0) :="00000000000000";		
	signal o2x : std_logic_vector(10 downto 0) :="00000000000";
	signal o24x: std_logic_vector(14 downto 0) :="000000000000000";
	signal o3x: std_logic_vector(10 downto 0) :="00000000000";
	signal o37x: std_logic_vector(15 downto 0) :="0000000000000000";	
	signal o36x: std_logic_vector(15 downto 0) :="0000000000000000"; 
	signal o113x: std_logic_vector(17 downto 0) :="000000000000000000";
	signal o201x: std_logic_vector(17 downto 0) :="000000000000000000";		

			 
begin

G1: process(clock,datain)
begin	
     if(clock'event and clock='1')then
     G1_t1x<=datain;
     G1_t2x<=datain(8) & datain & '0';
     G1_t8x<=datain(8) & datain & "000";
     G1_t16x<=datain(8) & datain & "0000";

     end if;
 
  end process G1;   
  
  
G2: process(clock,datain)
begin
    if(clock'event and clock='1')then
    G2_t1x<=G1_t1x;
    G2_t2x<=G1_t2x;
    G2_t8x<=G1_t8x;
    G2_t16x<=G1_t16x;
    G2_t3x<=G1_t2x+G1_t1x;
    G2_t7x<=G1_t8x-G1_t1x;
    G2_t9x<=G1_t8x+G1_t1x;
    G2_t17x<=G1_t16x+G1_t1x;
    end if;

end process G2;  

G3: process(clock,datain)
begin
    if(clock'event and clock='1')then
    G3_t1x<=G2_t1x;
    G3_t2x<=G2_t2x;
    G3_t8x<=G2_t8x;
    G3_t16x<=G2_t16x;
    G3_t3x<=G2_t3x;
    G3_t7x<=G2_t7x;
    G3_t9x<=G2_t9x;
    G3_t17x<=G2_t17x;
    G3_t12x<=G2_t3x(10) & G2_t3x & "00";
    G3_t14x<=G2_t7x(12) & G2_t7x & '0';
    G3_t24x<=G2_t3x(10) & G2_t3x & "000";
    G3_t28x<=G2_t7x(12) & G2_t7x & "00";
    G3_t36x<=G2_t9x(12) & G2_t9x & "00";
    G3_t112x<=G2_t7x(12) & G2_t7x & "0000";
    G3_t192x<=G2_t3x(10) & G2_t3x & "000000";
    end if;

end process G3;    

G4: process(clock,datain)
begin
    if(clock'event and clock='1')then
    G4_t2x<=G3_t2x;
    G4_t16x<=G3_t16x;
    G4_t3x<=G3_t3x;
    G4_t9x<=G3_t9x;
    G4_t17x<=G3_t17x;
    G4_t24x<=G3_t24x;
    G4_t36x<=G3_t36x;
    
    G4_t11x<=G3_t8x+G3_t3x;
    G4_t13x<=G3_t12x+G3_t1x;
    G4_t21x<=G3_t14x+G3_t7x;
    G4_t23x<=G3_t24x-G3_t1x;
    G4_t27x<=G3_t28x-G3_t1x;
    G4_t37x<=G3_t36x+G3_t1x;
    G4_t113x<=G3_t112x+G3_t1x;
    G4_t201x<=G3_t192x+G3_t9x;
    end if;
end process G4; 

G5: process(clock,datain)
begin
    if(clock'event and clock='1')then
    o6x<=G4_t3x & '0';
    o22x<=G4_t11x & '0';
    o54x<=G4_t27x & '0';
    o4x<=G4_t2x & '0';
    o32x<=G4_t2x & "0000";
    o256x<=G4_t2x & "0000000";
 
    o9x<=G4_t9x;
    o17x<=G4_t17x;
    o21x<=G4_t21x;
    o23x<=G4_t23x;
    o16x<=G4_t16x;
    o13x<=G4_t13x;
    o2x<=G4_t2x;
    o24x<=G4_t24x;
    o3x<=G4_t3x;
    o37x<=G4_t37x;
    o36x<=G4_t36x;
    o113x<=G4_t113x;
    o201x<=G4_t201x;   
 
    
    end if;
end process G5;
          
 ----------------------------------------------------------------     
 add:
process(clock)

 begin
      if(clock'event and clock='1')then      
      dout<=D(47)-o6x;
          
      D(47)<=D(46)-o9x;
      D(46)<=D(45)-o9x;
      D(45)<=D(44)-o4x;
      D(44)<=D(43)+o6x;
      D(43)<=D(42)+o17x;
      D(42)<=D(41)+o23x;
      D(41)<=D(40)+o21x;
      D(40)<=D(39)+o9x;
      D(39)<=D(38)-o6x;
      D(38)<=D(37)-o16x;
      D(37)<=D(36)-o13x;
      D(36)<=D(35)+o2x;
      D(35)<=D(34)+o22x;
      D(34)<=D(33)+o32x;
      D(33)<=D(32)+o24x;
      D(32)<=D(31)-o3x;
      D(31)<=D(30)-o37x;
      D(30)<=D(29)-o54x;
      D(29)<=D(28)-o36x;
      D(28)<=D(27)+o24x;
      D(27)<=D(26)+o113x;
      D(26)<=D(25)+o201x;
      D(25)<=D(24)+o256x;
      ------------------------------------------------------------------------------- 
      D(24)<=D(23)+o256x;
      D(23)<=D(22)+o201x;
      D(22)<=D(21)+o113x;
      D(21)<=D(20)+o24x;
      D(20)<=D(19)-o36x;
      D(19)<=D(18)-o54x;
      D(18)<=D(17)-o37x;
      D(17)<=D(16)-o3x;
      D(16)<=D(15)+o24x;
      D(15)<=D(14)+o32x;
      D(14)<=D(13)+o22x;
      D(13)<=D(12)+o2x;
      D(12)<=D(11)-o13x;
      D(11)<=D(10)-o16x;
      D(10)<=D(9)-o6x;
      D(9)<=D(8)+o9x; 
      D(8)<=D(7)+o21x;
      D(7)<=D(6)+o23x;
      D(6)<=D(5)+o17x;
      D(5)<=D(4)+o6x;
      D(4)<=D(3)-o4x;
      D(3)<=D(2)-o9x;
      D(2)<=D(1)-o9x;
      D(1)<="00000000000000000000"-o6x;
 	  end if;
end process add;

end a;