代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
www.eeworm.com/read/264704/11304000

sdo int_to_vector_suo_v.sdo

// Copyright (C) 1991-2007 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any o
www.eeworm.com/read/264704/11304016

sdo int_to_vector_suo_v.sdo

// Copyright (C) 1991-2007 Altera Corporation // Your use of Altera Corporation's design tools, logic functions // and other software and tools, and its AMPP partner logic // functions, and any o
www.eeworm.com/read/401363/11558555

v map_lpm_ram.v

module map_lpm_ram(dataout,datain,addr,we,inclk,outclk); input[15:0] datain; input[7:0] addr; input we,inclk,outclk; output[15:0] dataout; lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/346808/11720310

c spi.c

#include "2410addr.h" #include "spi.H" #define SPIDONTCARE (0xff) /* init as SPI-Master */ void spi_init(void) { int i; rGPECON&=0xf03fffff; rGPECON|=((1
www.eeworm.com/read/260276/11735151

vhd even_odd.vhd

library ieee; use ieee.std_logic_1164.all; entity even_odd is port( datain:in std_logic_vector(31 downto 0); par:out std_logic; clk:in std_logic ); end even_odd; architecture beh
www.eeworm.com/read/344792/11859884

v map_lpm_ram.v

module map_lpm_ram(dataout,datain,addr,we,inclk,outclk); input[15:0] datain; input[7:0] addr; input we,inclk,outclk; output[15:0] dataout; lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/257336/11933436

v map_lpm_ram.v

module map_lpm_ram(dataout,datain,addr,we,inclk,outclk); input[15:0] datain; input[7:0] addr; input we,inclk,outclk; output[15:0] dataout; lpm_ram_dq ram(.data(datain),.address(addr),.we(we),.i
www.eeworm.com/read/343298/11959343

asv conv_encode.asv

function [out]=Conv_encode(datain,length); data_u=uint16(datain); for i=1:6 dr(i)=uint16(0); end for j=1:length a=bitxor(data_u(j),dr(2)); a=bitxor(a,dr(3)); a=bitxor(a,dr(5));
www.eeworm.com/read/343298/11959420

m scrambler.m

function [out]=Scrambler(datain,length,seed_identifier); if isequal(seed_identifier,[0 0]) for i=1:15 reg=[0 0 1 1 1 1 1 1 1 1 1 1 1 1 1]; end elseif isequal(seed_identifier,[0 1])
www.eeworm.com/read/343298/11959567

m de_qpsk_mapping_plcp.m

function [out]=de_qpsk_mapping_plcp(datain,length); for i=1:length if(real(datain(i))>=0) temp((i-1)*2+1)=1; else temp((i-1)*2+1)=0; end if(imag(datain(i))>=0); tem